原句Converters CHAPTER 6: CONVERTERS INTRODUCTION 6.1 SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.3 DIGITAL-TO ANALOG CONVERTERS (DACs OR D/As) INTRODUCTION 6.3 KELVIN DIVIDER (STRING DACs) 6.4 SEGMENTED DACs 6.5 DIGITAL POTS 6.7 THERMOMETER (FULLY DECODED) DACs 6.9 BINARY WEIGHTED CURRENT SOURCES 6.12 R-2R LADDER 6.14 MULTIPLING DACs 6.18 SEGMENTED DACs 6.20 SIGMA-DELTA DACs 6.22 I/V CONVERTERS 6.23 DIFFERENTIAL TO SINGLE-ENDED CONVERSION TECHNIQUES 6.24 SINGLE-ENDED CURRENT-TO-VOLTAGE CONVERSION 6.27 DIFFERENTIAL CURRENT-TO-VOLTAGE CONVERSION 6.27 DIGITAL INTERFACES 6.28 DATA CONVERTER LOGIC: TIMING AND OTHER ISSUES 6.33 INTERPOLATING DACs (INTERPOLATING TxDACs) 6.33 RECONSTRUCTION FILTERS 6.35 SIN(X)/(X) (SINC) 6.36 INTENTIONALLY NONLINEAR DACs 6.37 SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.40 THE COMPARATOR: A 1-BIT ADC 6.44 SUCCESSIVE APPROXIMATION ADCs 6.45 FLASH CONVERTERS 6.50 SUBRANGING, ERROR CORRECTED, AND PIPELINED ADCs 6.52 SERIAL BIT-PER-STAGE BINARY AND GRAY CODED (FOLDING) ADCs 6.58 COUNTING AND INTEGRATING ADC ARCHITECTURES 6.64 CHARGE RUN-DOWN ADCs 6.65 RAMP RUN-UP ADCs 6.65 TRACKING ADCs 6.66 VOLTAGE-TO-FREQUENCY CONVERTERS (VFCs) 6.68 DUAL-SLOPE/MULTISLOPE ADCs 6.73 RESOLVER-TO-DIGITAL CONVERTERS (RDCs) AND SYNCHROS 6.76

原句BASIC LINEAR DESIGN SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES (cont.) REFERENCES 6.80 SECTION 6.3: SIGMA-DELTA (ΣΔ) CONVERTERS 6.85 HISTORICAL PERSPECTIVE 6.85 BASICS OF SIGMA-DELTA ADCs 6.90 IDLE TONE CONSIDERATIONS 6.96 HIGHER ORDER LOOP CONSIDERATIONS 6.98 MULTIBIT SIGMA-DELTA CONVERTERS 6.98 DIGITAL FILTER IMPLICATIONS 6.100 HIGH RESOLUTION MEASUREMENT SIGMA-DELTA ADCs 6.102 BAND-PASS SIGMA-DELTA CONVERTERS 6.107 SIGMA-DELTA DACs 6.108 SUMMARY 6.110 REFERENCES 6.111 SECTION 6.4: DEFINING THE SPECIFICATIONS 6.115 SECTION 6.5: DAC AND ADC STATIC TRANSFER FUNCTIONS AND DC ERRORS 6.117 SECTION 6.6: DATA CONVERTER AC ERRORS 6.129 NOISE IN PRACTICAL ADCs 6.131 EQUIVALENT INPUT REFERRED NOISE 6.131 NOISE-FREE (FLICKER-FREE) CODE RESOLUTION 6.132 DYNAMIC PERFORMANCE OF DATA CONVERTERS 6.133 INTEGRAL AND DIFFERENTIAL NONLINEARITY DISTORTION EFFECTS 6.133 HARMONIC DISTORTION, WORST HARMONIC, TOTAL HARMONIC DISTORTION (THD), TOTAL HARMONIC DISTORTION PLUS NOISE (THD + N) 6.135 SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD), SIGNAL-TO-NOISE RATIO (SNR) AND EFFECTIVE NUMBER OF BITS (ENOB) 6.136 ANALOG BANDWIDTH 6.137 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 6.138 TWO TONE INTERMODULATION DISTORTION (IMD) 6.141 MULTITONE SPURIOUS-FREE DYNAMIC RANGE 6.142 SECOND- AND THIRD-ORDER INTERCEPT POINTS, 1 dB COMPRESSION POINT 6.143 WIDEBAND CDMA (W-CDMA) ADJACENT CHANNEL POWER RATIO (ACPR) AND ADJACENT CHANNEL LEAKAGE RATIO (ADLR) 6.145 NOISE POWER RATIO (NPR) 6.146 NOISE FACTOR (F) AND NOISE FIGURE (NF) 6.149

原句Converters SECTION 6.6: DATA CONVERTER AC ERRORS (cont.) APERTURE TIME, APERTURE DELAY TIME, AND APERTURE JITTER 6.156 A SIMPLE EQUATION FOR THE TOTAL SNR OF AN ADC 6.160 ADC TRANSIENT RESPONSE AND OVERVOLTAGE RECOVERY 6.161 ADC SPARKLE CODES, METASTABLE STATES, AND BIT ERROR RATE (BER) 6.163 DAC DYNAMIC PERFORMANCE 6.167 DAC SETTLING TIME 6.167 GLITCH IMPULSE AREA 6.168 DAC SFDR AND SNR 6.170 MEASURING DAC SNR WITH AN ANALOG SPECTRUM ANALYZER 6.172 OTHER AC SPECIFICATIONS 6.173 REFERENCES 6.175 SECTION 6.7: TIMING SPECIFICATIONS 6.177 SECTION 6.8: HOW TO READ A DATA SHEET 6.181 THE FRONT PAGE 6.181 THE SPECIFICATION TABLES 6.181 THE ABSOLUTE MAXIMUMS 6.188 THE ORDERING GUIDE 6.189 PIN DESCRIPTION 6.191 DEFINING THE SPECIFICATIONS 6.192 EQUIVALENT CIRCUITS 6.193 THE GRAPHS 6.194 THE MAIN BODY 6.198 CIRCUIT DESCRIPTION 6.198 INTERFACE 6.199 REGISTER DESCRIPTION 6.201 APPLICATIONS CIRCUITS 6.202 EVALUATION BOARDS 6.203 SUMMARY 6.203 SECTION 6.9: CHOOSING A DATA CONVERTER 6.205 DETERMINE THE PARAMETERS 6.205 PRIORITIZING THE PARAMETERS 6.206 SELECTING THE PART 6.206

原句BASIC LINEAR DESIGN

原句CONVERTERS INTRODUCTION 6.1 CHAPTER 6: CONVERTERS Introduction There are two basic type of converters, digi tal-to-analog (DACs or D/As) and analog-todigital (ADCs or A/Ds).

原句Their purpose is fa irly straightforward.

原句In the case of DACs, they output an analog voltage that is a pr oportion of a reference voltage, the proportion based on the digital word applied.

原句In the case of the ADC, a digital representation of the analog voltage that is applied to the ADC s input is outputted, the representation proportional to a reference voltage.

原句In both cases the digital word is almost al ways based on a binarily weighted proportion.

原句The digital input or output is arranged in wo rds of varying widths, referred to as bits, typically anywhere from 6 bits to 24 bits.

原句In a binarily weighted system each bit is worth half of the bit to its left and twice the bit to its right.

原句The greater the number of bits in the digital word, the finer the reso lution.

原句These bits ar e typically arranged in groups of four, called bytes, for convenience.

原句For a better understandi ng of the relationship between th e digital domain and the analog domain please refer to the section on sampling theory.

原句As stated earlier, we shall look at the opera tion of converters primarily from a “black box” view.

原句We will concern ourselves less with the internal construction of the converter and more with its operation.

原句We cannot, ho wever, completely ignore the internal architecture because in many cases it is releva nt to operational advantages or limitations.

原句There are a number of works that cover the in ternal workings of th e converters in much more detail (see References).

原句Another point that should be kept in mind is the difference between accuracy and resolution.

原句The resolution of a converter is the number of bits in its digital word.

原句The accuracy is the number of those bits that m eet the specifications.

原句For instance, a DAC might have 16 bits of resolution, but might onl y be monotonic to 14 bits.

原句This means that the assured accuracy of the DAC will be no better than 14 bits.

原句Also, an audio ADC might have a digital word width of 16 bits, but the SNR may be only 70 dB.

原句This means that the accuracy will only be at the 12-bit level.

原句This is not to say that the other bits are irrelevant.

原句With further processing, typi cally filtering, often th e accuracy can be improved.

原句While these terms are similar and sometimes used interchangeably, the distinction between the two should be remembered.

原句We shall examine the DAC first.

原句BASIC LINEAR DESIGN 6.2

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.3 SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES Digital-to-Analog Converters (DACs or D/As) Introduction What we commonly refer to as a DAC today is typically quite a bit more.

原句The DAC will typically have the converter itself and a collection of support circuitry built into the chip.

原句The first DACs were board level designs, built from discrete components, including vacuum tubes as the switching elements.

原句Mono lithic DACs began to appear in the early ’70s.

原句These early examples were actually su b-blocks of the DAC.

原句An example of this would be the AD550, which was a 4 bit binarily weighted current source.

原句This current source block would be mated to a separate part, such as the AD 850, which contained a resistor array and CMOS switches.

原句Together these would form the basic DAC.

原句As we moved on in time these functions were integrated on the sa me die, additional digital circuitry, specifically latches to store the digital input, were added.

原句Then a second rank of latches was often added.

原句The purpose of the second rank was to allow the microprocessor or microcontroller to write to many DACs in a system and the updated them all at the same time.

原句The input rank of latches could al so be a shift register, which would allow a serial interface.

原句Figure 6.1: The Basic DAC DIGITAL INPUT VDD VSS GROUND (MAY BE INTERNALLY CONNECTED TO VSS) (ANALOG) REFERENCE INPUT DAC VREF DIGITAL INPUT VDD VSS GROUND (MAY BE INTERNALLY CONNECTED TO VSS) (ANALOG) REFERENCE INPUT DAC VREF

原句BASIC LINEAR DESIGN 6.4 On the back end, since the output of the DAC is often a current, an op amp is often added to perform the current-to-voltage (I/V) conversion.

原句On the front end a voltage reference is often added.

原句Process limitations did not allow the integration of all these sub-blocks to occur at once.

原句Initially, the processes used to make the va rious sub-blocks were not compatible.

原句The process that made the best switches was typi cally not the best for the amplifier and the reference.

原句As the processes became more advanced these limitations became less.

原句Today CMOS can make acceptable amplifiers a nd processes combining bipolar and CMOS together exist.

原句There are several advantages to including all this additional circuitry in one package.

原句The first is the obvious advantage of reducing th e chip count.

原句This reduces the size of the circuitry and increases the reliability.

原句Probably more important is that the circuit designer now doesn’t have to concern hi mself with the accuracy of se veral parts in a system.

原句The system is now one part and tested by the manufacturer as a unit.

原句Next we will look at the various DAC architectures.

原句When we refer to DACs here we are referring to the basic converter rather than the complete system.

原句Kelvin Divider (String DAC) The simplest structure of all is the Kelvin divider or string DAC as shown in Figure 6.2.

原句An N-bit version of this DAC simply consists of 2 N equal resistors in series and 2 N switches (usually CMOS), one between each node of the chain and the output.

原句The output is taken from the appropriate tap by closing ju st one of the switches (t here is some slight digital complexity involved in decoding to 1 of 2N switches from N-bit data).

原句This architecture is simple, has a voltage out put and is inherently monotonic—even if a resistor is accidentally shor t-circuited, output n cannot exceed output n + 1.

原句It is linear if all the resistors are equal, but may be made deliberately nonlinear if a nonlinear DAC is required.

原句The output is a voltage, but it has the disadvantage of ha ving a relatively large output impedance.

原句This output impedance is also code dependant (the impedance changes with changes to the digital input).

原句In many cases it will be beneficial to follow the output of the DAC with an op amp to buffer this output impedance and present a low impedance source to the following circuitry.

原句Since only two switches operate during a transition it is a low glitch architecture (the concept of glitch will be examined in a fo llowing section).

原句Also, the switching glitch is not code-dependent, making it ideal for low di stortion applications.

原句Because the glitch is constant regardless of the code transition, th e frequency content of the glitch is at the DAC update rate and its harmonics—not at the harmonics of the DAC output signal frequency.

原句The major drawback of the Kelvin DAC is the large num ber of resistors and switches required for high resolution.

原句There are 2 N resistors required, so a 10 bit DAC would require 1024 switches and resistors, a nd as a result it was not commonly used as a simple DAC architecture until the recent advent of very small IC feature sizes made it very practical for low and medium resolution (typically up to 10 bits) DACs.

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.5 Figure 6.2: Simplest Voltage-Output Thermometer DAC: The Kelvin Divider As we mentioned in the section on sampling th eory, the output of a DAC for an all 1s code is 1 LSB below the reference, so a Kelvin divider DAC intended for use as a general-purpose DAC has a resistor between the reference terminal and the first switch as shown in Figure 6.2.

原句Segmented String DACs A variation of the Kelvin divider is the segmented string DAC.

原句Here we reduce the number of resistors required by segmenting.

原句Figure 6.3 shows two varieties of segmented voltage-output DAC.

原句The architecture in Fi gure 6.3A is sometimes called a KelvinVarley Divider.

原句Since there are buffers be tween the first and second stages, the second string DAC does not load the first, and the re sistors in the second string do not need to have the same value as the resistors in the first.

原句All the resistors in each string, however, do need to be equal to each other or the DAC will not be linear.

原句The examples shown have 3-bit first and second stages but for the sa ke of generality, let us refer to the first (MSB) stage resolution as M-bits and the second (LSB) as K-bits for a total of N = M + K bits.

原句The MSB DAC has a string of 2 M equal resistors and a string of 2 K equal resistors in the LSB DAC.

原句As an example, if we make a 10-bit string DAC out of two 5-bit sections, each segment would have 2 5 or 32 resistors, for a total of 64, as opposed to the 1024 required for a standard Kelvin divider.

原句This is an obvious advantage.

原句3-TO-8 DECODER 3-BIT DIGITAL INPUT ANALOG OUTPUT VREF CIRCA 1920 SWITCHES WERE RELAYS OR VACUUM TUBES 8 TO SWITCHES R R R R R R R R

原句BASIC LINEAR DESIGN 6.6 Figure 6.3: Segmented Voltage-Output DACs Buffer amplifiers can have offset, of c ourse, and this can cause nonmonotonicity in a buffered segmented string DAC.

原句In the simpler configuration of a buffered Kelvin-Varley divider buffer (Figure 6.3A), buffer A is always “below” (at a lower potenti al than) buffer B, and the extra tap labeled “A” on the LSB string DAC is not necessary.

原句The data decoding is just two priority encoders.

原句But if the decoding of the MSB string DAC is made more complex so that buffer A can only be connected to the taps labeled “A” in the MSB string DAC, and buffer B to the taps labeled “B,” then it is not possible for buffer offsets to cause nonmonotonicity.

原句Of course, the LSB string DAC decoding must change direction each time one buffer “leapfrogs” the other, and taps A and B on the LSB string DAC are alternately not used—but this involves a fairly trivial increase in logic complexity and is justified by the increased performance.

原句Rather than using a second string of resist ors, a binary R-2R DAC can be used to generate the three LSBs as shown in Figure 6.3B.

原句This voltage-output DAC (Figure 6.3B) consists of a 3-bit string DAC followed by a 3-bit buffered voltage-mode ladder network.

原句Again the number of resistors require for the DAC is reduced.

原句An unbuffered version of the segmented stri ng DAC is shown in Figure 6.4.

原句This version is more clever in concept.

原句Here, the resistors in the two strings must be equal, except that the top resistor in the MSB string must be smaller—1/2 K of the value of the others—and the LSB string has 2 K – 1 resistors rather than 2 K.

原句Because there are no buffers, the LSB string appears in parallel with the resistor in the MSB string that it is switched across and loads it.

原句This drops the voltage across th at MSB resistor by 1 LSB of the LSB DAC— which is exactly what is required.

原句The output impedance of this DAC, being unbuffered, KELVIN-VARLEY DIVIDER ("STRING DAC") VREF VREF OUTPUT KELVIN DIVIDER AND R-2R LADDER NETWORK NOTE: MSB OF LADDER ON RIGHT IF THE LADDER NETWORK IS MONOTONIC, THE WHOLE DAC IS MONOTONIC OUTPUT (A) (B) A B A B A B A B A A BA B

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.7 varies with changing digital code.

原句This circ uit is intrinsically monotonic since it is unbuffered (and, of course, can be manufact ured on CMOS processes which make resistors and switches but not high precision amplifiers, so it may be cheaper as well).

原句Figure 6.4: Segmented Unbuffered String DACs Use Patented Architecture In order to understand this clever concept be tter, the actual voltages at each of the taps has been worked out and labeled for the 6- bit segmented DAC composed of two 3-bit string DACs shown in Figure 6.4.

原句The reader is urged to go through this simple analysis with the second string DAC conne cted across any other resist or in the first string DAC and verify the numbers.

原句A detailed mathematical analysis of the unbuffered segmented string DAC can be found in the relevant patent filed by Dennis Dempsey and Christopher Gorman of Analog Devices in 1997 (Reference 14).

原句Digital Potentiometers Another variation of the string DAC is the digital potentiometer.

原句A simple digital potentiometer is shown in Figure 6.5.

原句The major difference is that the lower arm of the potentiometer (terminal B) is not connected to ground, but is instead left floating .

原句The absolute values of the resistors in a Kelvin DAC typically are not critical.

原句They are limited by the available material.

原句They must, of course, be the same as each other.

原句In a digital potentiometer the end-to-end resistance is specified.

原句The accuracy of the end to end resistance is on the order of a R R R R R R R R R 8 VREF 63 64 VREF 63 64 VREF 55 64 VREF 55 64 VREF 54 64 VREF 54 64 VREF 53 64 VREF 53 64 VREF 52 64 VREF 52 64 VREF 51 64 VREF 51 64 VREF 50 64 VREF 50 64 VREF 49 64 VREF 49 64 VREF 48 64 VREF 48 64 VREF 40 64 VREF 40 64 VREF 32 64 VREF 32 64 VREF 24 64 VREF 24 64 VREF 16 64 VREF 16 64 VREF 8 64 VREF 8 64 VREF OUTPUT R R R R R R R 55 64 VREF 55 64 VREF 48 64 VREF 48 64 VREF Dennis Dempsey and Christopher Gorman, "Digital-to-Analog Converter," U.S.

原句Patent 5,969,657, filed July 27, 1997, issued October 19, 1999.

原句BASIC LINEAR DESIGN 6.8 mechanical potentiometer.

原句Digital potentiomet ers are typically available in end-to-end resistance values from 10 k Ω to 1 M Ω.

原句Lower values of end-to-end resistance are difficult since the on resistance of the CMOS switches is on the orde r of the resistor segment, so the linearity of the pot suffers at the low end.

原句Figure 6.5: A Slight Modification to a Kelvin DAC Yields a "Digital Potentiometer" The advantages to digital po tentiometers are many.

原句Even th e lowest resolution digital potentiometers have better setability than th eir mechanical counterparts.

原句Also, they are immune to mechanical vibration and oxi dation of the wiper contact.

原句Obviously, adjustments can be made without human intervention.

原句In most digital potentiometers the voltage on the input pins can not exceed the supplies (typically 3 V or 5 V) due to the CMOS switc hes used in their construction, but certain models are designed for ±15 V operation.

原句Another design feature on many of the digi tal potentiometers is that on power up (sometimes from an internal timer, sometimes c ontrolled by an extern al pin) the wiper is shorted to one of the terminals.

原句This is us eful since output on power up is undefined until it is written to.

原句Since it might take a while (relatively) for the micro-controller to initialize itself and then get around to initializing th e rest of the system , having the digital potentiometer in a known state can be useful .

原句Some digital potentiometers incorporate nonvolatile logic so that their settings are retained when they are turned off.

原句One time programmable (OTP) versions of digital potentiometers have become available.

原句Here the digital code is locked into the potentiometer once the setting had been determined.

原句The technology used is fuseable links.

原句A variat ion on this theme is the two 3-TO-8 DECODER 3-BIT DIGITAL INPUT TAP 8 TO SWITCHES R R R R R R R TERMINAL A TERMINAL B

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.9 times programeable (TTP) digital potentiometer .

原句This allows the nonv olatile settings to be modified one time.

原句The block diagram of a TTP digital potentiometer is shown in Figure 6.6.

原句Figure 6.6: Two Times Programmable (TTP) Digital Potentiometer Block Diagram Thermometer (Fully Decoded) DACs There is a current-output DAC architecture an alogous to a string DAC which consists of 2 N – 1 switchable current sources (which may be resistors and a voltage reference or may be active current sources) connected to an ou tput terminal.

原句This output must be at, or close to, ground.

原句Figure 6.7 show s a thermometer DAC which us e resistors connected to a reference voltage to generate the currents.

原句If active current sources are used as shown in Figure 6.8, the output may have more compliance (the allowable voltage on the output pin which still guarantees performance), and a resistive load is typically used to deve lop an output voltage.

原句Th e load resistor must be chosen so that at maximum output current the output terminal remains within its rated compliance voltage Once a current in a thermometer DAC is sw itched into the circuit by increasing the digital code, any further increases do not switch it out again.

原句The structure is thus inherently monotonic, irrespective of inaccura cies in the currents.

原句Again, like the Kelvin divider, only the advent of high density IC pr ocesses has made this architecture practical for general purpose medium resolution DAC s, although a slightly more complex version—shown in the next diagram—is quite widely used in high speed applications.

原句Unlike the Kelvin divider, this type of current-mode DAC does not have a unique name, although both types may be referred to as fully decoded DACs or thermometer DACs.

原句VDD GND SDA SCL AD0 AD1 W RDAC REGISTER ADDRESS DECODE SERIAL INPUT REGISTER BA FUSE LINKS12 /8

原句BASIC LINEAR DESIGN 6.10 Figure 6.7: The Simplest Current-Output Thermometer (Fully Decoded) DAC A DAC where the currents are switched between two output lines—one of which is often grounded, but may, in the more general case, be used as the inverted output—is more suitable for high speed applications because switching a current between two outputs is far less disruptive, and so causes a far lower glitch than simply switching a current on and off.

原句This architecture is shown in Figure 6.9.

原句Figure 6.8: Current Sources Improve the Basic Current-Output Thermometer DAC 3-BIT DIGITAL INPUT CURRENT OUTPUT INTO VIRTUAL GROUND (USUALLY AN OP-AMP I-V CONVERTER) VREF 3-TO-7 DECODER R R RRR RR TO SWITCHES 7 3-BIT DIGITAL INPUT 3-TO-7 DECODER I I III II CURRENT OUTPUT MAY HAVE COMPLIANCE OF 1 OR 2 V TO SWITCHES 7

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.11 Figure 6.9: High Speed Thermometer DAC with Complementary Current Outputs But the settling time of this DAC still varies with initial and final code, giving rise to intersymbol distortion (ISI).

原句This can be addressed w ith even more complex switching where the output current is returned to zero before going to its next value.

原句Note that although the current in the output is returned to zero it is not “turne d off”—the current is dumped to ground when it is not being used, rather than be ing switched on and off.

原句The techniques involved are too complex to disc uss in detail here but can be found in the references.

原句In the normal (linear) version of this DAC, all the currents are nominally equal.

原句Where it is used for high speed reconstruction, its linearity can also be improved by dynamically changing the order in which the currents are switched by ascending code.

原句Instead of code 001 always turning on current A; code 010 alwa ys turning on currents A and B, code 011 always turning on currents A, B, and C; etc. the order of turn-on relative to ascending code changes for each new data point.

原句This can be done quite easily with a little extra logic in the decoder.

原句The simplest way of achieving it is with a counter which increments with each clock cycle so that the orde r advances: ABCDEFG, BCDEFGA, CDEFGAB, etc., but this algorithm may give rise to spurious tone s in the DAC output.

原句A better approach is to set a new pseudo-random orde r on each clock cycle—this requires a little more logic, but even complex logic is now very cheap and easily implemented on CMOS processes.

原句There are other, even more comp lex, techniques which i nvolve using the data itself to select bits and thus turn current mi smatch into shaped noise.

原句Again they are too complex for a book of this sort.

原句(See references for a more detailed discussion).

原句3-BIT DIGITAL INPUT 3-TO-7 DECODER I I III II CURRENT OUTPUTS MAY HAVE COMPLIANCE OF 1 OR 2 V OUTPUT OUTPUT AB CD E F G TO SWITCHES7

原句BASIC LINEAR DESIGN 6.12 Binary Weighted Current Source The voltage-mode binary-weighted resistor DAC shown in Figure 6.10 is usually the simplest textbook example of a DAC.

原句Howeve r, this DAC is not inherently monotonic and is actually quite hard to manufacture successfully at high resolutions due to the large spread in component (resisto r) values.

原句In addition, the outpu t impedance of the voltagemode binary DAC changes with the input code.

原句Figure 6.10: Voltage-Mode Binary-Weighted Resistor DAC Current-mode binary weighted DACs are s hown in Figure 6.11A (resistor-based), and Figure 6.11B (current-source based).

原句An N-bit DAC of this type consists of N weighted current sources (which may simply be resist ors and a voltage refe rence) in the ratio 1:2:4:8:....:2N–1.

原句The LSB switches the 2 N–1 current, the MSB the 1 current, etc.

原句The theory is simple but the practical problems of manufacturing an IC of an economical size with current or resistor ratios of even 128:1 for an 8-bit DAC are enormous, especially as they must have matched temperature coeffici ents.

原句This architectur e is virtually never used on its own in integrated circuit DACs, although, again, 3-bit or 4-bit versions have been used as components in more complex structures.

原句For example, the AD550 mentioned at the beginning of this section is an example of a binary-weighted DAC.

原句If the MSB current is slightly low in value, it will be less than the sum of all the other bit currents, and the DAC will not be monotonic (t he differential nonlinearity of most types of DAC is worst at major bit transitions).

原句However, there is another binary-weighted DAC structure which has recently become widely used.

原句This uses binary-weighted cap acitors as shown in Figure 6.12.

原句The problem with a DAC using capacitors is that leakage ca uses it to lose its accuracy within a few milliseconds of being set.

原句This may make capacitive DACs unsuitable for generalpurpose DAC applications, but it is not a problem in successive approximation ADCs, R/8 R/4 R/2 R V V REF OUT MSBLSB Adapted from: B.

原句D. Smith, "Coding by Feedback Methods," Proceedings of the I.

原句R. E., Vol. 41, August 1953, pp.

原句1053-1058

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.13 since the conversion is complete in a few µs or less—long before leakage has any appreciable effect.

原句DIFFICULT TO FABRICATE IN IC FORM DUE TO LARGE RESISTOR OR CURRENT RATIOS FOR HIGH RESOLUTIONS VREF MSB LSB R 2R 4R 8R VREF MSB LSB R 2R 4R 8R MSB LSB I I 2 I 4 I 8 CURR ENT OUTPUTS INTO VIRTUAL GROUNDS (A) RESISTOR (B) CURR ENT SOURCE Figure 6.11: Current-Mode Binary-Weighted DACs Figure 6.12: Capacitive Binary-Weighted DAC in Successive Approximation ADC The use of capacitive charge redistribution DA Cs offers another advantage as well—the DAC itself behaves as a sample-and-hold circu it (SHA), so not only is an external SHA _ + _ + C/ 4C/ 2CC / 4 AIN VREF SIN SC S1 S2 S3 S4 BIT1 (MSB) BIT2 BIT3 (LSB) SWITCHES SHOWN IN TRACK (SAMPLE) MODE AA CTOTAL = 2C

原句BASIC LINEAR DESIGN 6.14 unnecessary with these ADCs, there is no need to allocate separate chip area for a separate integral SHA.

原句R-2R Ladder One of the most common DAC building-block st ructures is the R-2R resistor ladder network shown in Figure 3.15.

原句It uses resistor s of only two different values, and their ratio is 2:1.

原句An N-bit DAC requires 2N resistors, and they are quite easily trimmed.

原句There are also relatively few resistors to trim.

原句Figure 6.13: 4-Bit R-2R Ladder Network This structure is the basis of a large family of DACs.

原句Figure 6.14 is the block diagram of the AD7524, which is typical of a basic curr ent output CMOS DAC.

原句The diagram shows the structure of the DAC.

原句Figure 6.14: AD7524 CMOS DAC Block Diagram 2R 2R 2R 2R 2R RRR AD7524 DATA LATCHES AD7524 DATA LATCHES

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.15 The input impedance (basically the value of the resistors) is not a closely specified parameter.

原句The specified range is 4:1 (5 k Ω min, 20 k Ω max, although it is typically closer than that).

原句It is the relative accurac y, not the absolute accuracy of the resistors that is of interest.

原句In most applications the absolute value is not important.

原句Certain applications exist where the value does matter.

原句In these instances, the parts must be selected at test.

原句Note the extra resistor added at the R FEEDBACK pin.

原句This is designed to be the feedback resistor for the I/V op amp.

原句This resistor is trimmed along with the rest of the resistors so it tracks.

原句Also, since it is made of the same mate rial as the rest of th e resistors, therefore having the same temperature coe fficient, and is on the same s ubstrate, hence at the same temperature, it will track over temperature.

原句Figure 6.15 shows a more modern exampl e of a CMOS DAC, the AD7394.

原句Several trends are obvious here.

原句First off, the output is voltage, not current.

原句Advancements in process technology have allowed reasonable qual ity CMOS op amps to be created.

原句Also note the two ranks of latches.

原句The purpose of these latches is to allow the microcontroller to write to all converters in a system and then update them all at the same time.

原句This will be covered on more detail in a later section.

原句Note also the power on reset circuit.

原句Since the wake up st ate of a CMOS DAC is undefi ned and not repeatable, many modern DACs include a circuit to force the output to either half scale of minimum scale, depending on whether the intended application is unipolar or bipola r.

原句Probably the most obvious difference is that this is a multiple DAC package.

原句Shrinking device geometries have allowed more circuitry to be included, even with the smaller packages in use today.

原句Figure 6.15: AD7394 Quad CMOS DAC Block Diagram

原句BASIC LINEAR DESIGN 6.16 The previous examples were CMOS devices, that is to say, that the switches were implemented with CMOS switches.

原句The switches could also be implemented with bipolar transistors (BJT).

原句An example of this is the classic DAC-08.

原句Its block diagram is shown in Figure 6.16.

原句One major difference in the BJ T implementation is that the switch allows current in one direction, versus the CMOS switch, which can allow bidirectional current.

原句This limits the BJT DAC to 2-quadrant operation wh ile the CMOS version can be 4-quadrant.

原句Supplies tend to be different as well.

原句Figure 6.16: DAC-08 Block Diagram There are two ways in which the R-2R la dder network may be used as a DAC—known respectively as the voltage mode and the current mode (they are sometimes called “normal” mode and “inverted” mode, but as there is no consensus on whether the voltage mode or the current mode is the “normal” mode for a ladder network this nomenclature can be misleading, although in most cases th e current mode would be considered the “normal” mode).

原句Each mode has its advantages and disadvantages.

原句In the current-mode R-2R ladder DAC shown in Figure 6.17, the gain of the DAC may be adjusted with a series resistor at the V REF terminal, since in the current mode, the end of the ladder, with its code-independent impedance, is used as the V REF terminal; and the ends of the arms are switched between ground a nd an output line which must be held at ground potential.

原句The normal connection of a current-mode ladder network output is to an op amp’s inverting input (virtual ground), but stabilization of this op amp is complicated by the DAC output impedance variation with digital code.

原句VREF (+) 14 15 V+ V LC MSB B1 B2 B3 B4 B5 B6 B7 (LSB) B8 13 1 5 6 7 8 9 10 11 12 V–COMP 316 4 2 IOUT IOUT BIAS NETWORK CURRENT SWITCHES VREF (–) REFERENCE AMPLIFIER DAC08

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.17 Figure 6.17: Current-Mode R-2R Ladder Network DAC Current-mode operation has a larger switching glitch than voltage mode since the switches connect directly to th e output line(s).

原句However, sin ce the switches of a currentmode ladder network are always at ground potential, their de sign is less demanding and, in particular, their voltage ra ting does not affect the reference voltage rating.

原句If switches capable of carrying current in either direction (such as CMOS devices) are used, the reference voltage may have either polarity, or may even be ac.

原句Such a structure is one of the most common types used as a multiplying DAC (MDAC) which will be discussed later in this section.

原句Since the switches are always at, or very close to, ground potential, the maximum reference voltage may greatly exceed the logic voltage, provided the switches are makebefore-break—which they ar e in this type of DAC.

原句It is not unknown for a CMOS MDAC to accept a ±30 V reference (or even a 60-V peak-to-peak ac reference) while working from a single 5 V supply.

原句In the voltage mode R-2R ladder DAC show n in Figure 6.18, the “rungs” or arms of the ladder are switched between V REF and ground, and the output is taken from the end of the ladder.

原句The output may be taken as a voltage, but the output impedance is independent of code, so it may equally well be taken as a current into a virtual ground.

原句The voltage output is an advantage of this mo de, as is the constant output impedance, which eases the stabilization of any amplifie r connected to the output node.

原句Additionally, the switches switch the arms of the ladder between a low impedance V REF connection and ground, which is also, of course, low impedance, so capacitive glitch currents tend not to flow in the load.

原句On the other hand, the switc hes must operate over a wide voltage range (V REF to ground), which is difficult from a de sign and manufacturing viewpoint, and the reference input impedance varies widely with code, so that the refe rence input must be driven from a very low impedance.

原句In addi tion, the gain of the DAC cannot be adjusted by means of a resistor in series with the VREF terminal.

原句2R RRR 2R2R2R2R VREFVREF MSB LSB CURRENT OUTPUT INTO VIRTUAL GROUND << R * * GAIN TRIM IF REQUIRED

原句BASIC LINEAR DESIGN 6.18 Figure 6.18: Voltage-Mode R-2R Ladder Network DAC Probably the most important advantage to the voltage mode is that it allows single-supply operation.

原句This is because the op amp that is commonly used as I/V converter in the current mode converter is in the inverti ng configuration so w ould require a negative output for a positive input, assuming ground reference.

原句Of course you could bias everything up to a rail-splitter ground, but that introduces other issues into the system.

原句Multiplying DACs (MDACs) In most cases the reference to a DAC is a highly stable dc voltage.

原句In some instances, however, it is useful to have a variable reference.

原句The R-2R ladder structure using CMOS switches can easily handle a bipolar signal on its input.

原句Having the ability to have bipolar (positive and negative) signals on the i nput allows constructi on of 2-quadrant and 4-quadrant Multiplying DACs.

原句Figure 6.19 shows the schematic and Table I outlines the operation of a 2-quadrant MDAC and Figure 6.20 shows the schematic and Table II outlines the operation of a 4-quadrant MDAC for an 8-bit DAC.

原句DACs utilizing bipolar transistors as switc hes, such as the DAC-08 above, cannot accommodate bipolar signals on the referen ce.

原句Therefore they can only implement 2-quadrant MDACs.

原句In addition, the reference voltage can not go all the way to 0 V.

原句The maximum allowable range is typically from 10% to 100% of the allowable reference voltage range.

原句One of the main applications of the MDAC is as a variable gain amplifier, where the gain is controlled by the digital word applied to the MDAC.

原句2R R R R 2R 2R 2R 2R V V REF OUT MSBLSB Adapted from: B.

原句D. Smith, "Coding by Feedback Methods," Proceedings of the I.

原句R. E., Vol. 41, August 1953, pp.

原句1053-1058

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.19 Figure 6.19: 2-Quadrant Multiplying DAC Figure 6.20: 4-Quadrant Multiplying DAC

原句BASIC LINEAR DESIGN 6.20 The frequency response of the MDAC is lim ited by the parasitic ca pacitance across the switches in the off condition.

原句As the frequenc y goes up the impedance of the capacitors goes down, effectively bypassing the switch.

原句Th is reduces the off isolation at higher frequencies.

原句Typically the frequency response of an MDAC will be on the order of 1 MHz.

原句Segmented DACs So far we have considered mostly basic DAC architectures.

原句When we are required to design a DAC with a specific performance, it may well be that no single architecture is ideal.

原句In such cases, two or more DACs ma y be combined in a single higher resolution DAC to give the required performance.

原句Thes e DACs may be of the same type or of different types and need not each have the sa me resolution.

原句For example, the segmented string DAC is a segmented DAC where 2 Kelvin DACs are cascaded.

原句Typically, one DAC handles the MSBs, anothe r handles the LSBs, and their outputs are added in some way.

原句The process is known as “segmentation,” and these more complex structures are called “segmented DACs.” Th ere are many different types of segmented DACs and some, but by no means all, will be ill ustrated in the next few diagrams.

原句It is sometimes not obvious from looking at the data sheet that a particular DAC is segmented.

原句Figure 6.21: Segmented Current-Output DACs: (A) Resistor-Based, (B) Current-Source Based Very high speed DACs for video, communi cations, and other HF reconstruction applications are often built with arrays of fu lly decoded current sources.

原句The two or three RRRRRRR 2 R 2R 2R 2R 2R RRR VREF -3-BIT MSB THERMOMETER DAC 4-BIT R- 2R DAC CURRENT OUTPUT CURRENT II II I I I I 4 I 2 I 8 I 16 -3-BIT MSB THERMOMETER DAC 4- BIT BINARY DAC OUTPUT (A) (B) CURRENTSOURCE BASED IOUT IOUT IOUT IOUT RESISTOR BASED

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.21 LSBs may use binary-weighted current sources.

原句It is extremely important that such DACs have low distortion at high fr equency, and there are severa l important issues to be considered in their design.

原句Two examples of segmented current-output DAC structures are shown in Figure 6.21.

原句Figure 6.21A shows a resistor-based approach for the 7-bit DAC where the 3 MSBs are fully decoded, and the 4 LSBs are derived from an R-2R network.

原句Figure 6.21B shows a similar implementation using current sources .

原句The current source implementation is by far the most popular for today's high-speed reconstruction DACs.

原句It is also often desirable to utilize more than one fully decoded thermometer section to make up the total DAC.

原句Figure 6.22 shows a 6-bit DAC constructed from two fully decoded 3-bit DACs.

原句As previously discusse d, these current switches must be driven simultaneously from parallel latches in order to minimize the output glitch.

原句Figure 6.22: 6-Bit Current-Output Segmented DAC Based on Two 3-Bit Thermometer DACs The AD9775 14-bit, 160-MSPS (input)/400-MSPS (output) TxDAC ™ uses three sections of segmentation as shown in Figure 6.23.

原句Ot her members of the AD977x-family and the AD985x-family also use this same basic core.

原句The first 5 bits (MSBs) are fully decoded and drive 31 equally weighted current switches, each supplying 512 LSBs of current.

原句The next 4 bits are decoded into 15 lines which drive 15 current switches, each supplying 32 LSBs of current.

原句The 5 LSBs are latched and drive a traditional binary-weighted DAC which supplies 1 LSB per output level.

原句A total of 51 current switches and latches are required to implement this ultra low glitch architecture.

原句II I I III I 8 -3-BIT MSB THERMOMETER DAC 3- BIT LSB THERMOMETER DAC CURRENT OUTPUT CURRENT OUTPUT CURRENT OUTPUT I 8 I 8 I 8 I 8 I 8 I 8 IOUT IOUT

原句BASIC LINEAR DESIGN 6.22 Figure 6.23: AD9775 TxDAC 14-Bit CMOS DAC Core Decoding must be done before the new data is applied to the DAC so that all the data is ready and can be applied simultaneously to all the switches in the DAC.

原句This is generally implemented by using a separate parallel la tch for the individual switches in fully decoded array.

原句If all switches were to cha nge state instantaneously and simultaneously there would be no skew glitch—by very care ful design of propagation delays around the chip and time constants of switch re sistance and stray capacitance the update synchronization can be made very good, and hen ce the glitch-related distortion is very small.

原句Sigma-Delta DACs Sigma-Delta DACs will be discussed in detail in the Sigma-Delta section.

原句CLOCK 14-BIT LATCH 51-BIT LATCH 31 CURRENT SWITCHES 15 CURRENT 5 BINARY CURRENT SWITCHES BITS 1-5 DECODE 5-TO-31 BITS 6-9 DECODE 4-TO-15 5 5 15154 31 315 14 CURRENT OUTPUT FS = 2mA20mA SWITCHES I = 512 LSB I = 32 LSB I = 1 LSB 5 NOTE: Differential Outputs Not Shown

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.23 I/V Converters Modern IC DACs provide eith er voltage or current output s.

原句Figure 6.24 below shows three fundamental configurations, all with the objective of using an op amp for a buffered output voltage.

原句Figure 6.24: Buffering DAC Outputs with Op Amps Figure 6.24A shows a buffered voltage outpu t DAC.

原句In many cases, the DAC output can be used directly, without additional bufferi ng.

原句If an additional op amp is needed, it is usually configured in a noninverting mode, with gain determined by R1 and R2.

原句There are two basic methods for dealing with a current output DAC.

原句A direct method to convert the output curren t into a voltage is shown in Figure 6.24C.

原句This circuit is usually called a current-to-voltage converter, or I/V.

原句In this circuit, the DAC output drives the inverting input of an op amp, with the output voltage developed across the R2 feedback resistor.

原句In this approach the DAC output always operates at virtual ground (which may give a linearity improvement vis-à-vis Fig.

原句6.24B). In Figure 6.24B, a voltage is simply developed across external load resistor, RL.

原句This is typically done with high speed op amps.

原句An external op amp can be used to buffer and/or amplify this voltage if require d.

原句The output current is dumped into a resistor instead of into an op amp directly since the fast edges may exceed the slew rate of the amplifier and cause distortion.

原句Many DACs supply full-scal e currents of 20 mA or more, thereby allowing reasonable voltages to be developed ac ross fairly low value load resistors.

原句For instance, fast settling video DACs typically supply nearly 30 mA full-scale current, N + – VOUT N + – IOUT N + – IOUT (A) (B) (C) RL R2 R1 R2 R2 R1 VOUT 1 + R2 R1IOUT•RL –IOUT•R2 1 + R2 R1+N + – VOUT N + – IOUT N + – IOUT (A) (B) (C) RL R2 R1 R2 R2 R1 VOUT 1 + R2 R11 + R2 R1IOUT•RL –IOUT•R2 1 + R2 R11 + R2 R1+

原句BASIC LINEAR DESIGN 6.24 allowing 1 V to be developed acro ss a source and load terminated 75 Ω coaxial cable (representing a dc load of 37.5 Ω to the DAC output).

原句The general selection process for an op amp used as a DAC buffer is that the performance of the op amp should not compromise th e performance of the DAC.

原句The basic specifications of interest are DC accuracy, noise, settling time, bandwidth, distortion, etc.

原句Differential to Single-Ended Conversion Techniques A general model of a modern current output DAC is shown in Figure 6.25.

原句This model is typical of the AD976X and AD977X TxDAC series (see Reference 1).

原句Current output is more popular than voltage ou tput, especially at audio frequencies and above.

原句If the DAC is fabricated on a bipolar or BiCMOS process, it is likely that the output will sink current, and that the output impedance will be less than 500 Ω (due to the internal R/2R resistive ladder network).

原句On the other hand, a CMOS DAC is more likely to source output current and have a high output impedance, typically greater than 100 kΩ.

原句Figure 6.25: Model of High Speed DAC Output Another considera tion is the output compliance voltage— the maximum voltage swing allowed at the output in order for the DAC to maintain its linearity.

原句This voltage is typically 1 V to 1.5 V, but will vary de pending upon the DAC.

原句Best DAC linearity is generally achieved when driving a virtual ground, such as an op amp I/V converter.

原句Modern current output DACs usually have differential outputs, to achieve high CM rejection and reduce the even-order distorti on products.

原句Full-scale output currents in the range of 2 to 20 mA are common.

原句In most applications, it is desirable to convert the differe ntial output of the DAC into a single-ended signal, suitable for driving a coax line.

原句This can be readily achieved with an ROUT ROUT IFS –I I IOUT IOUT RSET ROUT ROUT IFS –I I IOUT IOUT RSET

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.25 RF transformer, provided low frequency resp onse is not required.

原句Figure 6.26 shows a typical example of this approach.

原句The hi gh impedance current output of the DAC is terminated differentially with 50 Ω, which defines the source impedance to the transformer as 50 Ω.

原句The resulting differential voltage drives the primary of a 1:1 RF transformer, to develop a single-ended voltage at the output of th e secondary winding.

原句The output of the 50 Ω LC filter is matched with the 50 Ω load resistor RL, and a fina l output voltage of 1 V p-p is developed.

原句Figure 6.26: Differential Transformer Coupling The transformer not only serves to convert the differential output into a single-ended signal, but it also isolates th e output of the DAC from the reactive load presented by the LC filter, thereby improving overall distortion performance.

原句Figure 6.27: Differential DC Coupled Output Using a Dual Supply Op Amp LC FILTER MINI-CIRCUITS T1-1T 1:1 RDIFF = 50Ω RLOAD = 50Ω VLOAD = ± 0.5V IOUT IOUT 0 TO 20mA 20 TO 0mA ± 10mACMOS DAC LC FILTER MINI-CIRCUITS T1-1T 1:1 RDIFF = 50Ω RLOAD = 50Ω VLOAD = ± 0.5V IOUT IOUT 0 TO 20mA 20 TO 0mA ± 10mACMOS DAC IOUT IOUT 0T O2 0 m A 20 TO 0mA CMOS DAC AD8055 + – +5V –5V 25Ω 25Ω 0V TO +0.5V +0.5V TO 0V CFILTER 500Ω 500Ω 1kΩ 1kΩ ±1 V f3dB = 1 2π •5 0Ω •CFILTER IOUT IOUT 0T O2 0 m A 20 TO 0mA CMOS DAC AD8055 + – +5V –5V 25Ω 25Ω 0V TO +0.5V +0.5V TO 0V CFILTER 500Ω 500Ω 1kΩ 1kΩ ±1 V f3dB = 1 2π •5 0Ω •CFILTER

原句BASIC LINEAR DESIGN 6.26 An op amp connected as a differential to singl e-ended converter can be used to obtain a single-ended output when frequency respons e to DC is required.

原句In Figure 6.28 the AD8055 op amp is used to achieve high bandwid th and low distortion (see Reference 2).

原句The current output DAC drives balanced 25 Ω resistive loads, thereby developing an outof-phase voltage of 0 V to +0.5 V at each out put.

原句The AD8055 is configured for a gain of 8, to develop a final single-ended ground-refere nced output voltage of 2 V p-p.

原句Note that because the output signal swings above and below ground, a dual-supply op amp is required.

原句The C FILTER capacitor forms a differential filter with the equivalent 50 Ω differential output impedance.

原句This filter reduces any sl ew induced distortion of the op amp, and the optimum cutoff frequency of the filter is determ ined empirically to give the best overall distortion performance.

原句A modified form of the Fi gure 6.26 circuit can also be operated on a single supply, provided the CM voltage of the op amp is se t to mid-supply (+2.5 V).

原句This is shown in Figure 6.28.

原句The output voltage is 2 V p-p cen tered around a CM voltage of +2.5 V.

原句This CM voltage can be either deve loped from the +5 V supply using a resistor divider, or directly from a +2.5 V voltage reference.

原句If the +5 V supply is used as the CM voltage, it must be heavily decoupled to prevent supply noise from being amplified.

原句IOUT IOUT 0T O2 0 m A 20 TO 0mA CMOS DAC AD8055 + – +5V 25Ω 25Ω 0V TO +0.5V +0.5V TO 0V CFILTER 500Ω 500Ω 2kΩ ±1 V f3dB = 1 2π •5 0Ω •CFILTER +2.5V +5V 2kΩ +2.5V REF 1kΩ SEE TEXT +5V IOUT IOUT 0T O2 0 m A 20 TO 0mA CMOS DAC AD8055 + – +5V 25Ω 25Ω 0V TO +0.5V +0.5V TO 0V CFILTER 500Ω 500Ω 2kΩ ±1 V f3dB = 1 2π •5 0Ω •CFILTER +2.5V +5V 2kΩ +2.5V REF 1kΩ+5V Figure 6.28: Differential DC Coupled Output Using a Single-Supply Op Amp

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.27 Single-Ended Current-to-Voltage Conversion Single-ended current-to-voltage conversion is easily performed using a single op amp as an I/V converter, as shown in Figure 6.29.

原句Th e 10 mA full-scale DAC current from the AD768 (see Reference 3) develops a 0 V to +2 V output voltage across the 200 Ω RF.

原句Driving the virtual ground of the AD8055 op amp minimizes any distortion due to nonlinearity in the DAC output impedance.

原句In fact, most high reso lution DACs of this type are factory trimmed using an I/V converter.

原句It should be recalled, however, that usi ng the single-ended output of the DAC in this manner will cause degradation in the CM rejection and increased second-order distortion products, compared to a differential operating mode.

原句Figure 6.29: Single-Ended I/V Op Amp Interface for Precision 16-bit AD768 DAC The C F feedback capacitor should be optimized for best pulse response in the circuit.

原句The equations given in the diagram should only be used as guidelines.

原句A more detailed analysis of this circuit is given in the References.

原句Differential Current-to-Differential Voltage Conversion If a buffered differential voltage output is required from a current output DAC, the AD813X-series of differential amplifiers can be used as shown in Figure 6.30.

原句IOUT IOUT 0 TO 10mA AD768 16-BIT BiCMOS DAC AD8055 + – +5V RF = 200Ω –5V RDAC||CDAC CF 0 TO +2.0V For RDAC ≈ RF, make CF ≈ CIN RDAC (CDAC + CIN) RF For RDAC >> RF, make CF ≈ CDAC + CIN 2π RF fu fu = Op Amp Unity Gain-Bandwidth Product IOUT IOUT 0 TO 10mA AD768 16-BIT BiCMOS DAC AD8055 + – +5V RF = 200Ω –5V RDAC||CDAC CF 0 TO +2.0V For RDAC ≈ RF, make CF ≈ CIN RDAC (CDAC + CIN) RF For RDAC >> RF, make CF ≈ CDAC + CIN 2π RF fu fu = Op Amp Unity Gain-Bandwidth Product

原句BASIC LINEAR DESIGN 6.28 The DAC output current is first converted into a voltage that is developed across the 25 Ω resistors.

原句The voltage is amplified by a fact or of 5 using the AD813 X.

原句This technique is used in lieu of a direct I/V conversion to prevent fast slewing DAC currents from overloading the amplifier and introducing distortion.

原句Care must be taken so that the DAC output voltage is within its compliance rating.

原句Figure 6.30: Buffering High Speed DACs using AD813X Differential Amplifier The V OCM input on the AD813X can be used to set a final output CM voltage within the range of the AD813X.

原句If transmission lines are to be driven at the output, adding a pair of 75 Ω resistors will allow this.

原句Digital Interfaces The earliest monolithic DACs contained little, if any, logic circuitry, and parallel data had to be maintained on the digital input to maintain the digital output.

原句Today almost all DACs are latched and data need only be written to them, not maintained.

原句Some even have nonvolatile latches and remember settings while turned off.

原句There are innumerable variatio ns of DAC digital input stru cture, which will not be discussed here, but the near ly all are described as “ double-buffered.” A double-buffered DAC has two sets of latches.

原句Data is initia lly latched in the first rank and subsequently transferred to the second as shown in Figure 6.31.

原句There are tw o reasons why this arrangement is useful.

原句The first is that it allows data to enter the DAC in many different ways.

原句A DAC without a latch, or with a single latch, must be loaded in parallel with all bits at once, since otherwise its output during loading may be totally different from what it was or what it is to become.

原句A double-buffered DAC, on the other hand, may be loaded with parallel data, or with serial data, or with 4-bit or 8-bit words, or wh atever, and the output will be IOUT IOUT 0 TO 20mA 0 TO +0.5V 20 TO 0mA +0.5 TO 0V CMOS DAC + – AD813X VOCM 2.49kΩ 2.49kΩ 5V p-p DIFFERENTIAL OUTPUT 25Ω 25Ω 499Ω 499Ω IOUT IOUT 0 TO 20mA 0 TO +0.5V 20 TO 0mA +0.5 TO 0V CMOS DAC + – AD813X VOCM 2.49kΩ 2.49kΩ 5V p-p DIFFERENTIAL OUTPUT 25Ω 25Ω 499Ω 499Ω

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.29 unaffected until the new data is completely loaded and the DAC receives its update instruction.

原句Figure 6.31: Double-Buffered DAC Permits Complex Input Structures and Simultaneous Update The other convenience of the double-buffered structure is that many DACs may be updated simultaneously: data is loaded into the first rank of each DAC in turn, and when all is ready, the output buffers of all the DACs are updated at once.

原句There are many DAC applications where the output of a number of DACs must change simultaneously, and the double-buffered structure allows this to be done very easily.

原句Most early monolithic high resolution DACs ha d parallel or byte-wide data ports and tended to be connected to pa rallel data buses and addre ss decoders and addressed by microprocessors as if they were very sm all write-only memories.

原句(Some parallel DACs are not write-only, but can have their contents read as well—this is convenient for some applications, but is not very common.) A DAC connected to a data bus is vulnerable to capacitive coupling of logic noise from the bus to the analog output Serial interfaces are less vulnerable to such noise (since fewer noi sy pins are involved), use fewer pins, and therefore take less board space, and are freque ntly more convenient for use with modern microprocessors, most of which have serial da ta ports.

原句Some, but not all, of such serial DACs have data outputs as well as data inputs so that several DACs may be connected in series and data clocked to them all from a single serial port.

原句This arrangement is often referred to as "daisy-chaining." Of course, serial DACs cannot be used wher e high update rates are involved, since the clock rate of the serial data would be too high.

原句Some very high speed DACs actually have two parallel data ports and use them alternat ely in a multiplexed fashion (sometimes this is called a “ping-pong” input) to reduce the data rate on each port as shown in Figure 6.32.

原句The alternate loading (ping-pong) DAC in the diagram loads from port A and port B alternately on the rising and fa lling edges of the clock, which must have a mark-space ratio close to 50:50.

原句The internal clock multiplier ensures that the DAC itself is updated with data A and data B alternatel y at exactly 50:50 time ratio, even if the external clock is not so precise.

原句OUTPUT DIGITAL INPUT INPUT STRUCTURE: MAY BE SERIAL, PARALLEL, BYTE-WIDE, ETC.

原句OUTPUT LATCH TRANSFERS DATA TO DAC - TIMING IS INDEPENDENT OF INPUT DAC OUTPUT STROBE - MAY GO TO MANY DACs fc = SAMPLING FREQUENCY

原句BASIC LINEAR DESIGN 6.30 Figure 6.32: Alternate Loading (Ping-Pong) High Speed DAC Historically integrated circuit logic circuitry (with the exception of emitter coupled logic or ECL) operated from 5 V supplies and had compatible logic levels—with a few exceptions 5 V logic would interface with othe r 5 V logic.

原句Today, with the advent of low voltage logic operating with supplies of 3.3 V, 2.7 V, or even less, it is important to ensure that logic interfaces are compatible.

原句There are several issues which must be considered—absolute maximum ratings, wors t case logic levels, and timing.

原句The logic inputs of integrated circuits generally have absolute maximum ratings, as do most other inputs, of 300 mV outside the power supply.

原句Note that these are instantaneous ratings.

原句If an IC has such a rating and is currently operating from a +5 V supply then the logic inputs may be between –0.3 V and +5.3 V—but if the supply is not present then that input must be between +0.3 V and –0.3 V, not the –0.3 V to +5.3 V which are the limits once the power is applied—ICs cannot predict the future.

原句The reason for the rating of 0.3 V is to ensure th at no parasitic diode inside the IC is ever turned on by a voltage outside the IC’s absolute maximum ra ting.

原句It is quite common to protect an input from such over-voltage with a Schottky diode clamp.

原句At low temperatures the clamp voltage of a Schottky diode may be a little more than 0.3 V, and so the IC may see voltages just outside it s absolute maximum rating.

原句Although, strictly speaking, this subjects the IC to stresses outside it s absolute maximum ratings and so is forbidden, this is an acceptable exception to the general rule provided the Schottky diode is at a similar temperature to the IC that it is protecting (say within ±10°C).

原句Some low voltage devices, however, have i nputs with absolute maximum ratings which are substantially greater than their supply voltage .

原句This allows such circuits to be driven by higher voltage logic without additional interface or clamp circuitry.

原句But it is important to read the data sheets and ensure that bot h logic levels and absolute maximum voltages are compatible for all combinations of high and low supplies.

原句This is the general rule when interfacing different low-voltage logic circuitry—it is always necessary to check both that at the lowest value of its power supply the logic 1 DATA MULTIPLEXER DAC LATCH DAC N N LATCH A LATCH B ×2 CLOCK MULTIPLIER N N N N DATA PORT A DATA PORT B CLOCK (50% DUTY CYCLE) OUTPUT OUTPUT

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.31 output from the driving circuit a pplied to its worst-case load is greater than the specified minimum logic 1 input for the receiving circuit, and that, again with its lowest value of power supply and with its output sinking maxi mum allowed current, the logic 0 output is less than the specified logic 0 input of the r eceiver.

原句If the logic sp ecifications of your chosen devices do not meet these criteria it will be necessary to select different devices, use different power supplies, or use additional interface circuitry to ensure that the required levels are available.

原句Note that additi onal interface circuitry will introduce extra delays in timing.

原句It is not sufficient to build an experimental se t-up and test it.

原句In ge neral, logic thresholds are generously specified and usually logic circuits will work correctly well outside their specified limits—but it is no t possible to rely on this in a production de sign.

原句At some point a batch of devices near the limit on low output swing will be required to drive some devices needing slightly more drive than usual—and will be unable to do so.

原句One of the latest developments in high sp eed logic interface is LVDS.

原句Low voltage differential signaling (LVDS) presents a solu tion to the high speed converter interface problem by mitigating the effects of CMOS single-ended interfaces and accommodating higher data rates.

原句The LVDS standard speci fies a p-p voltage swing of 350 mV around a common-mode voltage of 1.2 V, which facilita tes transmission of high-speed differential digital signals with balanced current, th ereby reducing the slew rate requirement.

原句Reducing the slew rate elimin ates the gradients that resu lt in noise from ground bounce that are present in conventional CMOS drivers.

原句Ground-bounce noise can couple back into sensitive analog circuits and degrade the converter's dynamic range.

原句Parallel LVDS interfaces enable much highe r data rates and optimum dyn amic performance, in highspeed data converters.

原句LVDS also offers some benefit in reduced EMI.

原句The EMI fields generated by the opposing currents will tend to cancel each other (for matched edge rates).

原句Trace length, skew, and discontinuities will reduce this benefit and should be avoided.

原句LVDS also offers simpler timing constraint s compared to a demuxed CMOS solution at similar data rates.

原句A demuxed databus re quires a synchronization signal that is not required in LVDS.

原句In demuxed CMOS buses, a clock equal to one-h alf the ADC sample rate is needed, adding cost a nd complexity, that is not requi red in LVDS.

原句In general, the LVDS is more forgiving and can lead to a simpler, cleaner design.

原句Figure 6.33: LVDS Output Levels The LVDS specification (IEEE Standard 1596.3) was developed as an extension to the 1992 SCI protocol (IEEE Standard 1596-1992).

原句Th e original SCI protocol was suitable for high speed packet transmissions in high end computing and used ECL levels.

原句350 mV+1.2 V 350 mV+1.2 V

原句BASIC LINEAR DESIGN 6.32 However, for low end and power sensitive applications, a new standard was needed.

原句LVDS signals were chosen because the volta ge swing is smaller than that of ECL outputs, allowing for lower power supplies in power sensitive designs.

原句Unlike CMOS, which is typically a voltage out put, LVDS is a current output technology.

原句LVDS outputs for high performance convert ers should be treated differently than standard LVDS outputs used in digital logic.

原句While standard LVDS can drive 1 m to 10 m in high speed digital applications (dependent on data rate), it is not recommended to let a high performance converters drive that distance.

原句It is recommended to keep the output trace lengths short (<2 in.), minimi zing the opportunity for any noise coupling onto the outputs from the adjacent circuitry, which may get back to the analog outputs.

原句The differential output traces should be routed close together, maximizing common-mode rejection with the 100 Ω termination resistor close to the receiver.

原句Users should pay attention to PCB trace lengths to minimize any delay skew.

原句A typical differential microstrip PCB trace cross section is shown in Figure 6.34.

原句Layout Guidelines Keep T W, TS, and D constant over the trace length Keep T S ~ < 2 TW Avoid use of vias where possible Keep D > 2 T S Avoid 90° bends if possible Design T W and TG for ~50 Ω Figure 6.34: PCB Trace Spacing Power supply decoupling is very important w ith these fast (<0.5 ns) edge rates.

原句A low inductance, surface-mount capacitor should be placed at every power supply and ground pin as close to the converter as possible.

原句Placing the decoup ling caps on the other side of the PCB is not recommended, since the via inductance will reduce the effective decoupling.

原句The differential Z O will tend to be slightly lower than twice the single-ended ZO of each conductor due to proximity effects—the Z O of each line should be designed to be slightly higher than 50 Ω.

原句Simulation can be used in cr itical applications to verify impedance matching.

原句In short runs, this should not be critical.

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.33 Data Converter Logic: Timing and other Issues It is not the purpose of this brief section to discuss logic architect ures, so we shall not define the many different data converter logic interface operati ons and their timing specifications except to note that data conve rter logic interfaces may be more complex than you expect—do not expect that because there is a pin with the same name on memory and interface chips it will behave in exactly the same way in a data converter.

原句Unfortunately, there is not a standard nomen clature for pin functionality, even for the same manufacturer.

原句The data sheet should always be consulted to determine the operation of all control pins.

原句Also some data conve rters reset to a know n state on power-up but many more do not.

原句But it is very necessary to consider general timing issues.

原句The new low voltage processes which are used for many modern data conver ters have a number of desirable features.

原句One which is often overlooked by users (but not by converter designers !) is their higher logic speed.

原句DACs built on olde r processes frequently had logic which was orders of magnitude slower than the microprocessors that they interfaced with and it was sometimes necessary to use separate buffers, or multiple WAIT instructions, to make the two compatible.

原句Today it is much more co mmon for the write times of DACs to be compatible with those of the fast logic with which they interface.

原句Nevertheless not all DACs are speed compatib le with all logic inte rfaces and it is still important to ensure that minimum data set- up times and write pulse widths are observed.

原句Again, experiments will often show that devi ces work with faster signals than their specification requires—but at the limits of te mperature or supply vol tage some may not and interfaces should be designed on the basis of specified rather than measured timing.

原句Interpolating DACs (Interpolating TxDACs) The concept of oversampling, to be discusse d in another section (on sampling theory), can be applied high speed DACs typically used in communications applications.

原句Oversampling relaxes the requirements on the output filter as well as increasing the SNR due to process gain.

原句Assume a traditional DAC is driven at an input word rate of 30 MSPS (see Figure 6.35A).

原句Assume the DAC output freq uency is 10 MHz.

原句The image frequency component at 30 MHz – 10 MHz = 20 MHz must be attenuated by the analog reconstruction filter, and the transition band of the filter is therefore 10 MHz to 20 MHz.

原句Assume that the image frequency must be attenuated by 60 dB.

原句The filter must therefore go from a passband of 10 MHz to 60 dB st opband attenuation over the transition band lying between 10 MHz and 20 MHz (one octave ).

原句Filter gives 6 dB attenuation per octave for each pole.

原句Therefore, a minimum of 10 poles is required to provide the desired attenuation.

原句This is a fairly aggressive f ilter and would involve high Q sections which would be difficult to align and manufacture.

原句Filters become even more complex as the transition band becomes narrower.

原句BASIC LINEAR DESIGN 6.34 Assume that we increase the DAC update ra te to 60 MSPS and insert a "zero" between each original data sample.

原句The parallel data stream is now 60 M SPS, but we must now determine the value of the zero-value data poi nts.

原句This is done by passing the 60 MSPS data stream with the added zeros through a di gital interpolation filter which computes the additional data points.

原句The response of th e digital filter relati ve to the 2-times oversampling frequency is shown in Fi gure 6.35B.

原句The analog antialiasing filter transition zone is now 10 MHz to 50 MHz (the first image occurs at 2f c – fo = 60 – 10 = 50 MHz).

原句This transition zone is a little greater than 2 octaves, impl ying that a 5-pole or 6-pole Butterworth filter is sufficient.

原句Figure 6.35: Analog Filter Requirements for fo = 10 MHz: (A) fc = 30 MSPS, and (B) fc = 60 MSPS The AD9773/AD9775/AD9777 (12-/ 14-/16-bit) series of Transmit DACs (TxDAC) are selectable 2×, 4×, or 8× oversampling inte rpolating dual DACs, and a simplified block diagram is shown in Figure 6.36.

原句These device s are designed to handle 12-/14-/16-bit input word rates up to 160 MSPS.

原句The output word rate is 400 MSPS maximum.

原句For an output frequency of 50 MHz, an input update rate of 160 MHz, and an oversampling ratio of 2×, the image frequency occurs at 320 MHz – 50 MHz = 270 MHz.

原句The transition band for the analog filter is therefore 50 MHz to 270 MHz.

原句Without 2× oversampling, the image frequency occurs at 160 MHz – 50 MHz = 110 MHz, and the filter transition band is 60 MHz to 110 MHz. fCLOCK = 30MSPS dB IMAGE 10 20 30 40 50 60 70 80 fo ANALOG LPF 10 20 30 40 50 60 70 80 IMAGE ANALOG LPF FREQUENCY (MHz) IMAGE IMAGEIMAGE IMAGE fo fCLOCK = 60MSPS dB A B fCLOCK = 30MSPS dB IMAGE 10 20 30 40 50 60 70 80 fo ANALOG LPF 10 20 30 40 50 60 70 80 IMAGE ANALOG LPF FREQUENCY (MHz) IMAGE IMAGEIMAGE IMAGE fo fCLOCK = 60MSPS dB A B

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.35 Figure 6.36: Oversampling Interpolating TxDAC Simplified Block Diagram Reconstruction Filters The output of a DAC is not a continuously vary ing waveform, but instead a series of dc levels.

原句This output must be passed through a filter to remove the high frequency components and smooth waveform into a more truly analog waveform.

原句The concept of filtering is discussed in more detail in Chapter 8.

原句In general, to preserve spectral purity, the images of the DAC output must be attenuated below the resolution of DAC.

原句To use the example sited above, we assume that the DAC output pass-band is 10 MHz.

原句The sample ra te is 30 MHz.

原句Theref ore the image of the pass-band that must be attenuated is 30 MH z – 10 MHz = 20 MHz.

原句This is the sample rate minus the pass-band frequency.

原句The DAC in this example is a 10-bit device, which would indicate a distortion level of −60 dB.

原句So a reconstructi on filter should reduce the image by 60 dB while not attenuating the fundamental at all.

原句Since a filter attenuates at 6 dB/pole, this would indicate that a 10 th order filter would be required.

原句There are several other considerations that must be taken into account.

原句First is that most filter cutoffs are measured at the −3 dB point.

原句Therefore, if we do not want the fundamental attenuated, some margin in the filter is required.

原句The graphs in the filter section will help illustrate this point .

原句This will cause the transition band to become narrower and thus the order of the filter to increase.

原句Secondly, there is a phenomenon called “sinc.” fo K•fcfc LATCH LATCH DAC LPF DIGITAL INTERPOLATION FILTER PLL N N N N TYPICAL APPLICATION: fc = 160MSPS fo = 50MHz K = 2 Image Frequency = 320 – 50 = 270MHz

原句BASIC LINEAR DESIGN 6.36 Sin(x)/(x) (sinc) The output of a D/A converter is not a continually varying wave form bit instead a series of DC levels.

原句The DAC puts out a dc level until it is told to put out a new level.

原句This is illustrated in Figure 6.37.

原句Figure 6.37: Output of a DAC The width of the pulses is 1/F S.

原句The spectrum of each pulse is the sin (x)/x curve.

原句This is also known as the sinc curve.

原句This response is added to the response of the reconstruction filter to provide the overall response of the converter.

原句This will cause an amplitude error as the output frequency appro aches the Nyquist frequency (F S/2).

原句The value of the sinc function is shown in Figure 6.38.

原句Some high speed DACs incorporate an inverse filter (in the digital domain) to compensate for this rolloff.

原句Figure 6.38: Sinc (sin x/x) Curve (Normalized to FS) dB ττ τ τ = 1 fs time volts ττ τ τ = 1 fs time volts -50.00 -45.00 -40.00 -35.00 -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 f 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 FREQUENCY dB

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.37 Intentionally Nonlinear DACs Thus far, we have emphasized the impor tance of maintaining good differential and integral linearity.

原句However, there are situations where ADCs and DACs which have been made intentionally nonlinear (but maintain ing good differential lin earity) are useful, especially when processing signals having a wide dynamic range.

原句One of the earliest uses of nonlinear data converters was in the digi tization of voice-band signals for pulse code modulation (PCM) systems.

原句Major contributio ns were made at Bell Labs during the development of the T1 carrier system.

原句The motive for the nonlinear ADCs and DACs was to reduce the total number of bi ts (and therefore the serial transmission rate) required to digitize voice channels.

原句Straight linear encodi ng of a voice channel required 11-bits or 12-bits at an 8 kSPS per channel sampling rate.

原句In the 1960s Bell Labs determined that 7-bit nonlinear encoding was sufficient, and later in the 1970s went to 8-bit nonlinear encoding for better performance.

原句The nonlinear transfer function allocates more quantization levels out of the total range for small signals and fewer for large amplitude signals.

原句In effect, this reduces the quantization noise associated with small si gnals (where it is most noticeable) and increases the quantization noise for larger signals (where it is less noticeable).

原句The term companding is generally used to describe this form of encoding.

原句The logarithmic transfer function chosen is re ferred to as the “Bell µ-255” standard, or simply “µ-law.” A similar standard developed in Europe is referred to as “A-law.” The Bell µ-law allows a dynamic range of about 40 00:1 using 8 bits, whereas an 8-bit linear data converter provides a range of only 256:1.

原句The first generation channel bank (D1) us ed temperature contro lled resistor-diode networks for “compressors” ahead of a 7-bit linear ADC in the transmitter to generate the logarithmic transfer functi on.

原句Corresponding resistor-diode “expandors” having an inverse transfer function followed the 7-b it linear DAC in the receiver.

原句The next generation D2 channel banks used nonlinear ADCs and DACs to accomplish the compression/expansion functions in a much mo re reliable and cost-effective manner and eliminated the need for the temperature-controlled diode networks.

原句In his 1953 classic paper, B.

原句D. Smith proposed that the transfer function of a successive approximation ADC utilizing a nonlinear internal DAC in the feedback path would be the inverse transfer function of the DAC (Reference 8).

原句The same basic DAC could therefore be used in the ADC and also for the reconstruction DAC.

原句Later in the 1960s and early 1970s, nonlinear ADC and DAC technology using piecewise linear approximations of the desired transfer function allowed low cost, high volume implementations (References 1823).

原句These nonlinear 8-bit, 8-kSPS data c onverters became popular telecommunications building blocks.

原句The nonlinear transfer functi on of the 8-bit DAC is firs t divided into 16 segments (chords) of different slopes—the slopes are determined by th e desired nonlinear transfer function.

原句The 4 MSBs determine the segment containing the desired data point, and the individual segment is further subdivided into 16 equal quantization levels by the 4 LSBs of the 8-bit word.

原句This is shown in Figure 6.39 for a 6-bit DAC, where the first three bits identify one of the eight possible chords, and each chord is further subdivided into eight

原句BASIC LINEAR DESIGN 6.38 equal levels defined by the 3 LSBs.

原句The 3 MSBs are generated using a nonlinear string DAC, and the 3 LSBs are generated using a 3-bit binary R-2R DAC.

原句Figure 6.39: Nonlinear 6-Bit Segmented DAC In 1982, Analog Devices introduced the LOGDAC ™ AD7111 monolithic multiplying DAC featuring wide dynamic range using a logarithmic transfer function.

原句The basic DAC in the LOGDAC is a linear 17-bit voltage-m ode R-2R DAC preceded by an 8-bit input decoder (A functional diagram of the LOGDAC is shown in Figure 6.40).

原句The LOGDAC can attenuate an anal og input signal, V IN, over the range 0 dB to 88.5 dB in 0.375 dB steps.

原句The degree of attenuation across the DAC is determined by a nonlinear-coded 8-bit word applied to the onboard decode logic.

原句This 8-bit word is mapped into the appropriate 17-bit word which is then appl ied to a 17-bit, R-2R ladder.

原句In addition to providing the logarithmic transfer function, the LOGDAC al so acts as a full four-quadrant multiplying DAC.

原句With the introduction of high resolution lin ear ADCs and DACs, the method used in the LOGDAC is widely used today to implement various nonlinear transfer functions such as the µ-law and A-law companding functions required for telecommunications and other applications.

原句Figure 6.41 shows a general bloc k diagram of the modern approach.

原句The µ-law or A-law companded input data is mappe d into data points on the transfer function of a high resolution DAC.

原句This mapping can be easily accomplished by a simple lookup table in either hardware, software, or firmware.

原句A similar nonlinear ADC can be constructed by digitizing the analog input signal using a high resolution ADC and mapping the data points into a shorter word us ing the appropriate transfer function.

原句A big advantage of this method is that the transfer curve does not have to be approximated with straight line segments as in the earlier method, thereby providing more accuracy.

原句VREF NONLINEAR DIVIDER OUTPUT VREF R 2R 4R 8R 16R 32R 64R 128R 001000 010000 011000 100000 101000 110000 111000 111111 R-2R DAC DIGITAL CODE DYNAMIC RANGE = 2048:1 (LINEARLY CODED 6-BIT DYNAMIC RANGE = 64:1) = 2.048V LSB 1mV LSB 2mV LSB 4mV LSB 8mV LSB 16mV LSB 32mV LSB 64mV LSB 128mV

原句CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.39 Figure 6.40: AD7111 LOGDAC (Released 1982) Figure 6.41: General Nonlinear DAC 2R RRR 2R2R2R2R MSB LSB VIN IOUT AGND RFB M-BIT LINEAR DAC DECODE LOGIC (LOOKUP TABLE) M-BIT LATCH N-BITS INPUT DATA VOUT M-BITS M-BITS M > N DECODE LOGIC CAN BE HARDWARE, SOFTWARE, OR FIRMWARE LOW RESOLUTION NONLINEARLY CODED DATA HIGH RESOLUTION LINEAR DAC NONLINEAR ANALOG OUTPUT

原句BASIC LINEAR DESIGN 6.40 SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES The basic ADC function is shown in Figure 6.42.

原句This could also be referred to as a quantizer.

原句Most ADC chips also include some of the support circui try, such as clock oscillator for the sampling clock, referen ce (REF), the sample and hold function, and output data latches.

原句In addition to these basic functions, some ADCs have additional circuitry built in.

原句These functions could include multiplexers, sequencers, auto-calibration circuits, programmable gain amplifiers (PGAs), etc.

原句Figure 6.42: Basic ADC Function Similar to DACs, some ADCs use external references and have a reference input terminal, while others have an output from an internal reference.

原句In some instances, the ADC may have an internal reference that is pinned out through a resistor.

原句This connection allows the reference to be filtered (using the internal R and an external C) or by allowing the internal reference to be overdriven by an external reference.

原句The AD789X family of parts is an example of ADC that use this type of connection.

原句The simplest ADCs, of course, have neither—the reference is on the ADC chip and has no external connections.

原句If an ADC has an internal reference, its ov erall accuracy is specified when using that reference.

原句If such an ADC is used with a perfectly accurate external reference, its absolute accuracy may actually be worse than when it is operated w ith its own internal reference.

原句This is because it is trimmed for absolute accuracy when working with its own actual reference voltage, not with the nomi nal value.

原句Twenty years ago it was common for converter references to have accuracies as poor as ±5% since these references were trimmed for low temperature coefficient rather than absolute accuracy, and the inaccuracy of the reference was compensated in the gain trim of the ADC itself.

原句Today the problem is much less severe, but it is st ill important to check for possible loss of VDD VSS GROUND (MAY BE INTERNALLY CONNECTED TO VSS) ADC ANALOG INPUT VREF DIGITAL OUTPUT SAMPLING CLOCK EOC, DATA READY, ETC.

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.41 absolute accuracy when using an external reference with an ADC which has a built-in one.

原句ADCs which have reference terminals must, of course, specify their behavior and parameters.

原句If there is a reference input the first specification will be the reference input voltage—and of course this has two values , the absolute maximum rating, and the range of voltages over which the ADC performs correctly.

原句Most ADCs require that their reference volta ge is within quite a narrow range whose maximum value is less than or equal to the ADC's V DD.

原句The reference input terminal of an ADC may be buffered as shown in Figure 6.43, in which case it has input impedance (usually high) and bias current (usually low) specifications, or it may connect directly to the ADC.

原句In either case, the transient currents developed on the reference input due to the internal conversion process need good decoupling with external low inductance cap acitors.

原句Good ADC data sheets recommend appropriate decoupling networks.

原句Figure 6.43: ADC with Reference and Buffer The reference output may be buffered or unbuffered.

原句If it is buffered, the maximum output current will probably be specified.

原句In general such a buffer will have a unidirectional output stage whic h sources current but does not allow current to flow into the output terminal.

原句If the buffer does have a push-pull output stage (not as common), the output current will probably be defined as ±(SOME VALUE) mA.

原句If the reference output is unbuffered, the output impedance may be specified, or the data sheet may simply advise the use of a high input impedance external buffer.

原句There are some instances where the power supply is the reference.

原句In these cases it is imperative to make sure the power supply is clean.

原句VDD VSS GROUND (MAY BE INTERNALLY CONNECTED TO VSS) ADC ANALOG INPUT VREF VOLTAGE REFERENCE Any, all or none of these pins may be connected internally or brought off the chip.

原句BUFFER AMP DATA OUTPUT SAMPLING CLOCK EOC, DATA READY, ETC.

原句BASIC LINEAR DESIGN 6.42 The sampling clock input is a critical function in an ADC and a source of some confusion.

原句It could truly be the sampling clock.

原句This frequency would typically be several times higher than the sampling rate of the converter.

原句It could also be a convert start (or encode) command which would happen once per conversion.

原句Pipeline architecture devices and sigma delta ( Σ-Δ) converters are continuously converting and have no convert start command.

原句Regardless of the ADC, it is extremely important to read the data sheet and determine exactly what the external clock requirements are, because they can vary widely from one ADC to another.

原句At some point after the assertion of the sampling clock, the output data is valid.

原句This data may be in parallel or serial format depending upon the ADC.

原句Early successive approximation ADCs such as the AD574 si mply provided a STATUS output (STS) which went high during the conversion, and retu rned to the low state when the output data was valid.

原句In other ADCs, this line is variously called busy, end-of-conversion (EOC), data ready, etc.

原句Regardless of the ADC, ther e must be some method of knowing when the output data is valid—and again, the data sheet is where this information can always be found.

原句Another detail which can cau se trouble is the differen ce between EOC and DRDY (data ready).

原句EOC indicates that conve rsion has finished, DRDY that data is available at the output.

原句In some ADCs, EOC functions as DRDY—in others, data is not valid until several tens of nanoseconds after the EOC has become valid, and if EOC is used as a data strobe, the results will be unreliable.

原句There are one or two other pr actical points which are worth remembering about the logic of ADCs.

原句On power-up, many ADCs do not have logic reset circuitry and may enter an anomalous logical state.

原句Severa l conversions may be necessar y to restore their logic to proper operation so: (a) the first few conversio ns after power-up should never be trusted, and (b) control outputs (EOC, data ready, etc. ) may behave in unexpected ways at this time (and not necessarily in the same way at each power-up), and (c) care should be taken to ensure that such anomalous behavior cannot cause system latch-up.

原句For example, EOC (end-of-conversion) should not be used to in itiate conversion if there is any possibility that EOC will not occur until th e first conversion has taken place, as otherwise initiation will never occur.

原句Some low-power ADCs now have power-sav ing modes of operation variously called standby, power-down, sleep, etc.

原句When an ADC comes out of one of these low-power modes, there is a certain recovery time re quired before the ADC can operate at its full specified performance.

原句The data sheet should therefore be carefully studied when using these modes of operation.

原句As a final example, some ADCs use CS (Chip Select) edges to reset internal logic, and it may not be possible to perform another conve rsion without asserti ng or reasserting CS (or it may not be possible to read the same data twice, or both).

原句For more detail, it is important to read th e whole data sheet before using an ADC since there are innumerable small logic variations fr om type to type.

原句Unfortunately, many data

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.43 sheets are not as clear as one might wish, so it is also important to understand the general principles of ADCs in order to interpret data sheets correctly.

原句That is one of the purposes of this section.

原句There are a couple of general trend in ADCs that should be addressed.

原句The first is the general trend toward lower s upply voltages.

原句This is partia lly due to the processes, particularly CMOS, which are used to ma nufacture the chips.

原句Increasing demand for speed has driven the feature size of the processes down.

原句This typically results in lower breakdown voltages for the transistors.

原句This, in turn, requires lower supply voltages.

原句Very few new parts are developed with the legacy ±15 V supplies and ±10 V input range.

原句Since the input signal range of the ADCs is shrinking, there is also a trend towards differential inputs.

原句This helps improve the dynamic range of a converter, typically by 6 dB.

原句There could be even further improvement since the common-mode ground referenced noise is rejected.

原句In many cases the differential input can be driven single endedly (with the resultant reduction of SNR) .

原句Occasionally the REF input might also be differential.

原句BASIC LINEAR DESIGN 6.44 The Comparator: A 1-Bit ADC A comparator is a 1-bit ADC (see Figure 6.44).

原句If the input is above a threshold, the output has one logic value, below it has an other.

原句There is no ADC architecture which does not use at least one comparator of some sort.

原句So while a 1 bit ADC is of very limited usefulness it is a building block for other architectures.

原句Figure 6.44: The Comparator: A 1-Bit ADC Comparators used as building blocks in ADCs need good resolution which implies high gain.

原句This can lead to uncont rolled oscillation when the differential input approaches zero.

原句In order to prevent this, hysteresis is often added to comparators using a small amount of positive feedback.

原句Figure 6.44 shows the effects of hysteresis on the overall transfer function.

原句Many comparators have a millivolt or two of hysteresis to encourage “snap” action and to prevent local feedback from causing instability in the transition region.

原句Note that the resolution of the comparat or can be no less th an the hysteresis, so large values of hysteresis are generally not useful. + – DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT LATCH ENABLE DIFFERENTIAL ANALOG INPUT COMPARATOR OUTPUT "0" "1" 0 VHYSTERESIS

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.45 Successive Approximation ADCs The successive approximation ADC has been the mainstay of data acquisition for many years.

原句Recent design improvements have extended the sampling frequency of these ADCs into the megahertz region.

原句The basic successive approximation ADC is shown in Figure 6.45.

原句It performs conversions on command.

原句On the asserti on of the CONVERT START command, the sample-and-hold (SHA) is placed in the hold mode, and all the bits of the successive approximation register (SAR) are reset to “0 ” except the MSB which is set to “1.” The SAR output drives the internal DAC.

原句If the DAC output is greater than the analog input, this bit in the SAR is reset, otherwise it is left set.

原句The next most significant bit is then set to “1.” If the DAC output is greater than th e analog input, this bit in the SAR is reset, otherwise it is left set.

原句The process is repe ated with each bit in turn.

原句When all the bits have been set, tested, and reset or not as a ppropriate, the contents of the SAR correspond to the value of the analog input, and the c onversion is complete.

原句These bit “tests” can form the basis of a serial output version SAR-based ADC.

原句Figure 6.45: Basic Successive Approximation ADC (Feedback Subtraction ADC) The fundamental timing diagram for a typi cal SAR ADC is shown in Figure 6.46.

原句The end of conversion is generally indicated by an end-of-convert (EOC), data-ready (DRDY), or a busy signal (actually, not-BUSY indicates end of conversion).

原句The polarities and name of this signal may be different for different SAR ADCs, but the fundamental concept is the same.

原句At the be ginning of the conversi on interval, the signal goes high (or low) and remains in that state until the conversion is completed, at which time it goes low (or high).

原句The trailing edge is generally an indi cation of valid output SHA CONTROL LOGIC: SUCCESSIVE APPROXIMATION REGISTER (SAR)DAC TIMING CONVERT START EOC, DRDY, OR BUSY OUTPUT ANALOG INPUT COMPARATOR

原句BASIC LINEAR DESIGN 6.46 data, but the data sheet should be carefully studied—in some ADCs additional delay is required before the output data is valid.

原句Figure 6.46: Typical SAR ADC Timing An N-bit conversion takes N steps.

原句It would seem on superficial examination that a 16-bit converter would have twice the conversion time of an 8-bit one, but this is not the case.

原句In an 8-bit converter, the DAC must settle to 8-bit accuracy before the bit decision is made, whereas in a 16-bit converter, it must settle to 16-bit accuracy, which takes a lot longer.

原句In practice, 8-bit successive approximation ADCs can convert in a few hundred nanoseconds, while 16-bit ones will generally take several microseconds.

原句While there are some variations, the fundame ntal timing of most SAR ADCs is similar and relatively straightforward.

原句The convers ion process is init iated by asserting a CONVERT START signal.

原句This signal is typically named something like CONVST or CS.

原句This signal is a usually a negative-goi ng pulse whose positive-going edge actually initiates the conversion.

原句The internal sample-and-hold (SHA) amplifier is placed in the hold mode on this edge, and th e various bits are determined using the SAR algorithm.

原句The negative-going edge of the CONVST pulse causes a signal typically called EOC (End Of Conversion) or BUSY to go high.

原句Wh en the conversion is complete, the BUSY line goes low (or EOC goes high), indicating the completion of the conversion process.

原句In most cases the trailing edge of the BUSY line can be used as an indication that the output data is valid and can be used to strobe the output data into an external register.

原句There may also be other control lines.

原句A nd sometimes control lines have dual function.

原句This is primarily done when the chip is pin limited.

原句Because of the many variations in terminology and design, the individual data sh eet should always be consulted when using a specific ADC.

原句CONVST CONVERSION TIME SAMPLE X SAMPLE X+1 SAMPLE X+2 DATA X DATA X+1 OUTPUT DATA EOC, BUSY EOC, BUSY TRACK/ ACQUIRE CONVERSION TIME TRACK/ ACQUIRE

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.47 It should also be noted that some SAR ADCs require an external high frequency clock in addition to the CONVERT START command.

原句In most cases, there is no need to synchronize the two.

原句The frequency of the exte rnal clock, if required, generally falls in the range of 1 MHz to 30 MHz depending on the conversion time and resolution of the ADC.

原句Other SAR ADCs have an internal os cillator which is used to perform the conversions and only require the CONVE RT START command.

原句Because of their architecture, SAR ADCs generally allow singl e-shot conversion at any repetition rate from dc to the converter's maximum conversion rate.

原句Notice that the overall accuracy and linearity of the SAR ADC is determined primarily by the internal DAC.

原句Until recently, most precision SAR ADCs used laser-trimmed thin-film DACs to achieve the desired accuracy and linearity.

原句The thin-fil m resistor trimming process adds cost, and the thin-film resistor values may be affected when subjected to the mechanical stresses of packaging.

原句For these reasons, switched capacitor (or ch arge-redistribution) DACs have become popular in newer SAR ADCs.

原句Th e advantage of the switched capacitor DAC is that the accuracy and linearity is primarily dete rmined by photolithography, which in turn controls the capacitor plate area and the capacitance as well as matching.

原句In addition, small capacitors can be placed in parallel with the main capacitors which can be switched in and out under control of autocalibration routines to achieve high accuracy and linearity without the need for thin-film laser trimming.

原句Temperature tracking between the switched capacitors can be better than 1 ppm/ºC, thereby offering a high degree of temperature stability.

原句Figure 6.47: 3-Bit Switched Capacitor DAC _ + _ + C/ 4C/ 2CC / 4 AIN VREF SIN SC S1 S2 S3 S4 BIT1 (MSB) BIT2 BIT3 (LSB) SWITCHES SHOWN IN TRACK (SAMPLE) MODE AA CTOTAL = 2C

原句BASIC LINEAR DESIGN 6.48 A simple 3-bit capacitor DAC is shown in Figure 6.47.

原句The switches are shown in the track, or sample mode where the analog input voltage, A IN, is constantly charging and discharging the parallel combina tion of all the capacitors.

原句The hold mode is initiated by opening SIN, leaving the sampled analog input vo ltage on the capacitor array.

原句Switch S C is then opened allowing th e voltage at node A to move as the bit switches are manipulated.

原句If S1, S2, S3, a nd S4 are all connected to ground, a voltage equal to –A IN appears at node A.

原句Connecting S1 to V REF adds a voltage equal to V REF/2 to –A IN.

原句The comparator then makes the MSB bit decision, an d the SAR either leaves S1 connected to VREF or connects it to ground depending on the comparator output (which is high or low depending on whether the voltage at node A is negative or positive, respectively).

原句A similar process is followed for the remaini ng two bits.

原句At the end of the conversion interval, S1, S2, S3, S4, and S IN are connected to A IN, SC is connected to ground, and the converter is ready for another cycle.

原句Note that the extra LSB capacitor (C/4 in the case of the 3-bit DAC) is required to make the total value of the capacitor array equal to 2C so that binary division is accomplished when the individual bit capacitors are manipulated.

原句The operation of the capacitor DAC (cap DAC ) is similar to an R-2R resistive DAC.

原句When a particular bit capacitor is switched to V REF, the voltage divider created by the bit capacitor and the total array cap acitance (2 C) adds a voltage to node A equal to the weight of that bit.

原句When the bit capacito r is switched to ground, the same voltage is subtracted from node A.

原句An example of charge redistribution successive approximation ADCs is Analog Devices’ PulSAR™ series.

原句The AD7677 is a 16-bit, 1-MSPS, PulSAR, fully differential, ADC that operates from a single 5 V power supply (see Figure 6.48).

原句The part contains a high speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports.

原句The AD7677 is hardware factory calibrated and comprehensively tested to ensure such ac pa rameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity.

原句It features a very high sampling rate mode (Warp) and, for asynchronous conversion rate applications, a fast mode (Normal) and, for low power applications, a reduced power mode (Impulse ) where the power is scaled with the throughput.

原句The operation of a successive approximation ADC is as follows.

原句Using Figure 6.49 as an example, one side of the balance is loaded with half scale (in this case 32 lbs.).

原句Call this the proof mass.

原句The test mass is then put on the other side of the balance.

原句If the test mass is greater, as it is in this case, the proof ma ss is retained, otherwise it is discarded.

原句Next a proof mass equal to ¼ scale is added.

原句Again, if the test mass is still greater the proof mass is retained, otherwise it is rejected.

原句It the example it is rejected.

原句This process is continued, each time cutting the proof mass in half, until the desired resolution is reached.

原句The proof masses are added up.

原句This will equal the mass of the test mass, to the resolution of the test.

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.49 Figure 6.48: AD7677 16-Bit 1-MSPS Switched Capacitor PulSAR ADC In a SAR ADC the proof mass is a voltage provided by the DAC.

原句It is compared to the input, corresponding to the test mass, by the co mparator.

原句Keeping track of output of each test and setting the DAC is accomplished by the successive approximation register.

原句The digital output is basically serial in natu re, but SAR ADCs are ge nerally available in both serial and parallel output formats.

原句Figure 6.49: Successive Approximation ADC Algorithm XXXTEST IS X ≥ 32 ?

原句YES Î RETAIN 32 Î 1 ASSUME X = 45 IS X ≥ (32 +16) ?

原句NO Î REJECT 16 Î 0 IS X ≥ (32 +8) ?

原句YES Î RETAIN 8 Î 1 IS X ≥ (32 +8 + 4) ?

原句YES Î RETAIN 4 Î 1 IS X ≥ (32 +8 + 4 + 2) ?

原句NO Î REJECT 2 Î 0 IS X ≥ (32 +8 + 4 + 2 + 1) ?

原句YES Î RETAIN 1 Î 1 X = 32 + 8 + 4 + 1 = 45 10 = 1011012TOTALS:

原句BASIC LINEAR DESIGN 6.50 Flash Converters Flash ADCs (sometimes called parallel ADCs) are the fastest t ype of ADC and use large numbers of comparators.

原句An N- bit flash ADC consists of 2 N resistors and 2 N–1 comparators arranged as in Figure 6.50.

原句Each comparator has a reference voltage which is 1 LSB higher than that of the one below it in the chain.

原句For a given input voltage, all the comparators below a certain point will have their input voltage larger than their reference voltage and a “1” lo gic output, and all the compar ators above that point will have a reference voltage larger than the input voltage and a “0 ” logic output.

原句The 2 N–1 comparator outputs therefore be have in a way analogous to a mercury thermometer, and the output code at this point is sometimes called a thermometer code.

原句Since 2 N–1 data outputs are not really practical, they are pr ocessed by a decoder to generate an N-bit binary output.

原句Figure 6.50: 3-Bit All-Parallel (Flash) Converter The input signal is applied to all the comparat ors at once, so the th ermometer output is delayed by only one comparator delay from the input, and the encoder N-bit output by only a few gate delays on top of that, so the process is very fast.

原句However, the architecture uses large numbers of resist ors and comparators and is limited to low resolutions, and if it is to be fast, each co mparator must run at relatively high power levels.

原句Hence, the problems of flash ADCs include limited resolution, high power dissipation because of the large number of high speed comparators (especially at sampling rates greater than 50 MSPS), and relatively large (and therefore expensive) chip sizes.

原句In addition, the resistance of the reference resistor chain must be kept low to supply N R PRIORITY ENCODER AND LATCH ANALOG INPUT DIGITAL OUTPUT +VREF R R R R R 0.5R STROBE 1.5R

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.51 adequate bias current to the fast comparators, so the voltage reference has to source quite large currents (typically > 10 mA).

原句Each comparator has a voltage -variable junction capacitance, and this signal-dependent capacitance results in most flash ADCs havi ng reduced ENOB and higher distortion at high input frequencies.

原句For this reason, most flash converters must be driven with a wideband op amp which is tolerant to the cap acitive load presented by the converter as well as high speed transients developed on the input.

原句Power dissipation is always a big considera tion in flash converters, especially at resolutions above eight bits.

原句A clever t echnique was used AD9410 10-bit, 210 MSPS ADC called interpolation to minimize the number of preamp lifiers in the flash converter comparators and also reduce the power (2.1 W).

原句The method is shown in Figure 6.51 (see reference).

原句Figure 6.51: “Interpolating” Flash Reduces the Number of Preamplifiers by Factor of Two The preamplifiers (labeled “A1,” “A2,” etc.) are low-gain g m stages whose bandwidth is proportional to the tail currents of the differen tial pairs.

原句Consider the case for a positivegoing ramp input which is initially below th e reference to AMP A1, V1.

原句As the input signal approaches V1, the differential output of A1 approaches zero (i.e., A = A ), and the decision point is reached.

原句The output of A1 dr ives the differential input of LATCH 1.

原句As the input signals continues to go positive, A continues to go positive, and B begins to go negative.

原句The interpolated decision point is determined when A = B .

原句As the input continues positive, the third decision point is reached when B = B .

原句This novel architecture reduces the ADC input capacitanc e and thereby minimizes its change with signal level and the associated distortion.

原句The AD9410 also uses an input sample-andhold circuit for improved ac linearity.

原句B V1A = A2 LATCH STROBE ANALOG INPUT ANALOG INPUT DECODE LATCH 2 LATCH 1A LATCH 1 A B V2 V1 A A1 + + - - B B B B V1A V1 A A A A V2 V1 + V2 2 AD9410: 10-Bits, 210MSPS

原句BASIC LINEAR DESIGN 6.52 Subranging, Error Corrected, and Pipelined ADCs A basic, two-stage N-bit subranging ADC is shown in Figure 6.52.

原句The ADC is based on two separate conversions—a coarse conversion (N1 bits) in the MSB sub-ADC (SADC) followed by a fine conversion (N2 bits) in the LSB sub-ADC.

原句Early subranging ADCs nearly always used flash converters as building blocks, but a number of recent ADCs utilize other architectures for the individual ADCs.

原句The conversion process begins placing the sample-and-hold in the hold mode followed by a coarse N1-bit sub-ADC (SADC) conversion of the MSBs.

原句The digital outputs of the MSB converter drive an N1-bit sub-DAC (SDAC ) which generates a coarsely quantized version of the analog input signal.

原句The N1-bit SDAC output is subtracted from the held analog signal, amplified, and applied to th e N2-bit LSB SADC.

原句The amplifier provides gain, G, sufficient to make the “residue” signal exactly fill the input range of the N2 SADC.

原句The output data from the N1 SADC and the N2 SADC are latched into the output registers yielding the N-bit digital output code, where N = N1 + N2.

原句Figure 6.52: N-bit Two-Stage Subranging ADC In order for this simple subranging architecture to work satisfactorily, both the N1 SADC and SDAC (although they only have N1 bits of resolution) must be better than N-bits accurate.

原句The residue signal offset and gain must be adjusted such that it precisely fills the range of the N2 SADC as shown in Figur e 3.66A.

原句If the residue signal drifts by more than 1 LSB (referenced to the N2 SADC), th en there will be missi ng codes as shown in Figure 3.66B where the residue signal enters the out-of-range regions labeled “X” and “Y.” Any nonlinearity or drift in the N1 SADC will also cause missing codes if it exceeds 1 LSB referenced to N-bits.

原句In practice, an 8-bit subranging ADC w ith N1 = 4 bits and N2 = 4 bits represents a realistic limit to th is architecture in order to maintain no missing codes over a reasonable operating temperature range.

原句SAMPLE AND HOLD Σ + – OUTPUT REGISTER ANALOG INPUT DATA OUTPUT, N-BITS = N1 + N2 CONTROL SAMPLING CLOCK See: R.

原句Staffin and R. Lohman, "Signal Amplitude Quantizer," U.S.

原句Patent 2,869,079, Filed December 19, 1956, Issued January 13, 1959 RESIDUE SIGNAL N1 MSBs N2 LSBs GN1-BIT SADC N1-BIT SDAC N2-BIT SADC

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.53 0 1 23 2N1–12N1–2 MISSING CODES MISSING CODES R=R A N G E OF N2 SADC X R Y (A) IDEAL N1 SADC (B) NONLINEAR N1 SADC 012 3 Figure 6.53: Residue Waveforms at Input of N2 Sub-ADC When the interstage alignment is not correct, missing codes will appear in the overall ADC transfer function as shown in Figure 6.54.

原句If the residue signal goes into positive overrange (the “X” region), the output first “sticks” on a code and then “jumps” over a region leaving missing codes.

原句The reverse occurs if the residue signal is negative overrange.

原句Figure 6.54: Missing Codes Due to MSB SADC Nonlinearity or Interstage Misalignment ANALOG INPUT DIGITAL OUTPUT MISSING CODES MISSING CODES "STICKS" "JUMPS" "JUMPS" "STICKS"

原句BASIC LINEAR DESIGN 6.54 In order to reliably achieve higher than 8-bit resolution us ing the subranging approach, a technique generally referred to as digital corrected subranging , digital error correction , overlap bits, redundant bits, etc. is utilized.

原句Figure 6.55 shows two methods that can be used to design a pipeline stage in a subranging ADC.

原句Figure 6.55A shows two pipelin ed stages which use an interstage T/H in order to provide interstage gain and give each stage the maximum possible amount of time to process the signal at its input.

原句In Figure 6.55B a multiplying DAC is used to provide the appropriate amount of interstage gain as well as the subtraction function.

原句Figure 6.55: Generalized Pipeline Stages in a Subranging ADC with Error Correction The term “pipelined” architectur e refers to the ability of one stage to process data from the previous stage during any given clock cycle.

原句At the end of each pha se of a particular clock cycle, the output of a given stage is passed on to the next stage using the T/H functions and new data is shifted into the stage.

原句Of course this means that the digital outputs of all but the last stage in the “pipeline” must be stored in the appropriate number of shift registers so that the digital data arriving at the co rrection logic corresponds to the same sample.

原句Figure 6.56 shows a timing diagram of a typi cal pipelined subranging ADC.

原句Notice that the phases of the clocks to the T/H amplifiers are alternated from stage to stage such that when a particular T/H in the ADC enters th e hold mode it holds the sample from the preceding T/H, and the preceding T/H returns to the track mode.

原句The held analog signal is passed along from stage to stage until it reaches the final stage in the pipelined ADC— in this case, a flash converter.

原句When operating at high sampling rates, it is critical that the differential sampling clock be kept at a 50% duty cycle for optimum performance.

原句Duty SADC N1 BITS SDAC N1 BITST/H + – T/H + – + – Σ + – SADC N2 BITS SDAC N2 BITS Σ + – SADC N1 BITS S MDAC N1 BITST/H + – T/H + – T/H + – SADC N2 BITS S MDAC N2 BITS (A) (B) TO ERROR CORRECTING LOGIC TO ERROR CORRECTING LOGIC T/H, G

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.55 cycles other than 50% affect all the T/H am plifiers in the chain—some will have longer than optimum track times and shorter than optimum hold times; while others suffer exactly the reverse condition.

原句Several newe r pipelined ADCs including the 12-bit, 65MSPS AD9235 and the 12-bit, 210-MSPS AD9430 have on-chip clock conditioning circuits to control the internal duty cycle wh ile allowing some variation in the external clock duty cycle.

原句Figure 6.56: Clock Issues in Pipelined ADCs The effects of the “pipeline” delay (sometimes called latency) in the output data as shown in Figure 6.57 for the AD9235 12-bit 65-MSPS ADC where there is a 7-clock cycle pipeline delay.

原句Figure 6.57: Typical Pipelined ADC Timing for AD9235 12-Bit, 65-MSPS ADC PIPELINE DELAY (LATENCY) = 7 CLOCK CYCLES FLASH CLOCK CLOCK VIN T INPUT T/H STAGE 1 T/H STAGE 2 T/H STAGE 3 T/H HT HT HT H H CLOCK INPUT T/H STAGE 1 STAGE 2 STAGE 3 FLASH THTHTH TH H HTHTHTT THTHTHTH H HTHTHTT DATA OUT DATA OUT DATA OUT DATA OUT THTHTHT H T H T HT PIPELINE DELAY

原句BASIC LINEAR DESIGN 6.56 Note that the pipeline delay is a function of the number of stages and the particular architecture of the ADC under consideration—the data sheet should always be consulted for the exact details of the relationship be tween the sampling clock and the output data timing.

原句In many applications the pipeline dela y will not be a problem, but if the ADC is inside a feedback loop the pipeline delay may cause inst ability.

原句The pipeline delay can also be troublesome in multiplexed applications or when operating the ADC in a "singleshot" mode.

原句Other ADC architectures—such as successive approximation—may be better suited to these types of applications.

原句The pipelined error correcting ADC has become very popular in modern ADCs requiring wide dynamic range and low levels of distortion.

原句There are many possible ways to design a pipelined ADC, and we will now look at just a few of the tradeoffs.

原句Figure 6.58A shows a pipelined ADC designed with identical stages of k-bits each.

原句This architecture uses the same core hardware in each stage, offers a few other advantages, but does necessarily optimize the ADC for best possible performan ce.

原句Figure 6.58B shows the simplest form of this architecture where k = 1.

原句Figure 6.58: Basic Pipelined ADC with Identical Stages In order to optimize performance at the 12-bit level, for example, 1-bit per stage pipeline is more commonly used with a multibit fron t-end and back-end ADC as shown in Figure 6.59.

原句Another less popular type of error corrected subra nging architecture is the recirculating subranging ADC.

原句The concept is similar to the error corrected subranging architecture previously discussed, but in this architectur e, the residue signal is recirculated through a single ADC and DAC stage using switches and a programmable gain amplifier (PGA).

原句T/H k-BIT ADC k-BIT DAC Σ + – 2k T/H k-BIT ADC k-BIT DAC Σ + – 2k T/H k-BIT ADC T/H 1-BIT ADC 1-BIT DAC Σ + – 2 T/H 1-BIT ADC 1-BIT DAC Σ + – 2 T/H 1-BIT ADC k k k MSBs LSBs MSB LSB (A) k-BITS PER STAGE (B) 1-BIT PER STAGE VIN VIN

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.57 The major problem with this technique is the PGA.

原句Its gain bandwidth product will limit the frequency response at higher gains.

原句Al so matching of the various gains could be problematic.

原句Figure 6.59: Multibit and 1-Bit Pipelined Core Combined Figure 6.60: Kinniment, et. al., 1966 Pipelined 7-bit, 9-MSPS Recirculating ADC Architecture T/H k-BIT ADC k-BIT DAC Σ + – 2k T/H 1-BIT ADC 1-BIT DAC Σ + – 2 T/H k MSBs T/H 1-BIT ADC 1-BIT DAC Σ + – 2 m-BIT ADC LSBs 1-BIT PIPELINED STAGES VIN SAMPLE AND HOLD PGAΣ 3-BIT FLASH ADC 3-BIT DAC + – REG.

原句REG. REG. REG. REG.

原句REG. ADDER OUTPUT REGISTER CONTROL ANALOG INPUT SAMPLING CLOCK Adapted from: D.J.

原句Kinniment, D. Aspinall, and D.B.G.

原句Edwards, "High-Speed Analogue-Digital Converter," IEE Proceedings, Vol.

原句113, pp. 2061-2069, Dec.

原句1966 DATA OUTPUT

原句BASIC LINEAR DESIGN 6.58 Serial Bit-Per-Stage Binary and Gray Coded (Folding) ADCs Various architectures exist for performing A/D conversion using one stage per bit.

原句Figure 6.61 shows the overall concept.

原句In fact, a multistage subranging ADC with one bit per stage and no error correction is one form as previously discussed.

原句In this approach, the input signal must be held cons tant during the entire conversion cycle.

原句There are N stages, each of which has a bit output and a residue output.

原句The residue output of one stage is the input to the next.

原句The last bit is detected with a single comparator as shown.

原句Figure 6.61: Generalized Bit-Per-Stage ADC Architecture Figure 6.62: Single-Stage Transfer Function for Binary ADC ANAL OG INPU T SHA STAGE 1 STAGE 2 DE COD E L OGI C A ND OUT PUT RE GIS TERS + -BIT 1 MSB BIT 2 VREF N R1 R2 STAGE N-1 BIT N-1 BIT N LSB B.

原句D. Smith, "An Unusual Electronic Analog-Digital Conversion Method," IRE Transactions on Instrumentation, June 1956, pp.

原句155-160. INPUT INPUTRESIDUE +VR +VR -VR -VR 0 0 RESIDUE+VR -VR G = 2 + - Σ BIT OUTPUT (BINARY CODE) SWITCH POSITION SHOWN FOR NEGATIVE INPUT t t

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.59 The basic stage for performing a single binary bit conversion is shown in Figure 6.62.

原句It consists of a gain-of-two amplifier, a comparator, and a 1-bit DAC.

原句Assume that this is the first stage of the ADC.

原句The MSB is simp ly the polarity of the input, and that is detected with the comparator which also controls the 1-bit DAC.

原句The 1-bit DAC output is summed with the output of the gain-of-two amplifier.

原句The resulting residue output is then applied to the next stage.

原句In order to better understand how the circuit works, the diagram shows the residue output for the case of a linear ramp input voltage which traverses the entire ADC range, –V R to +VR.

原句Notice that the polarity of the residue output determines the binary bit output of the next stage.

原句A simplified 3-bit serial-binary ADC is shown in Figure 6.63, and the residue outputs are shown in Figure 6.64.

原句Again, the case is shown for a linear ramp input voltage whose range is between –V R and +V R.

原句Each residue output signa l has discontinuities which correspond to the point where the comparat or changes state and causes the DAC to switch.

原句The fundamental problem with this arch itecture is the discontinuity in the residue output waveforms.

原句Adequate se ttling time must be allowed for these transients to propagate through all the stages and settle at the final comp arator input.

原句As presented here, the prospects of making this architecture operate at high speed are dismal.

原句However using the 1.5-bit-per stage pipelined architect ure previously discussed in this section makes it much more attractive at high speeds.

原句Figure 6.63: 3-Bit Serial ADC with Binary Output Although the binary method is disc ussed in his paper, B.

原句D. Smith also describes a much preferred bit-per-stage archit ecture based on absolute value amplifiers (magnitude amplifiers, or simply MagAMPs™).

原句This scheme has often been referred to as serialGray (since the output coding is in Gray code), or folding converter because of the shape of the transfer function.

原句Performing the conversion using a transfer function that produces an initial Gray code output has the advantage of minimizing discontinuities in the residue output waveforms and offers the potential of operating at much higher speeds than the binary approach.

原句ANAL OG INPU T SHA STAGE 1 STAGE 2 OUTPUT REGISTER + - BIT 1 BIT 2 BIT 3 ±VR 3 R1 R2ANALOG INPUT OUTPUT REGISTER

原句BASIC LINEAR DESIGN 6.60 Figure 6.64: Input and Residue Waveforms of 3-Bit Binary Ripple ADC The basic folding stage is shown functiona lly in Figure 6.65 along with its transfer function.

原句The input to the stage is assumed to be a linear ramp voltage whose range is between –V R and +V R.

原句The comparator detects the pol arity of the input signal and provides the Gray bit output fo r the stage.

原句It also determin es whether the overall stage gain is +2 or –2.

原句The reference voltage V R is summed with the switch output to generate the residue signal which is applied to the ne xt stage.

原句The polarity of the residue signal determines the Gray bit for the next stage.

原句The transfer function for the folding stage is also shown in Figure 6.65.

原句Figure 6.65: Folding Stage Functional Equivalent Circuit 000 001 010 011 100 101 110 111 INPUT R1 R2 –VR –VR –VR +VR +VR +VR 0 0 0 t t t BINARY CODE +VR –VR +VR –VR INPUT G = +2 INPUT RESIDUE +VR +VR -VR -VR 0 0 RESIDUE VR + - BIT OUTPUT (GRAY CODE) G = -2 Σ SWITCH POSITION SHOWN FOR NEGATIVE INPUT t t

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.61 A 3-bit MagAMP folding ADC is shown in Figure 6.66, and the corresponding residue waveforms in Figure 6.67.

原句As in the case of the binary ripple ADC, the polarity of the residue output signal of a stag e determines the value of the Gray bit for the next stage.

原句The polarity of the input to the first stage de termines the Gray MSB; the polarity of R1 output determines the Gray bit-2; and the polarity of R2 output determines the Gray bit-3.

原句Notice that unlike the binary ripple ADC, ther e is no abrupt transi tion in any of the folding stage residue output waveforms.

原句This makes operation at high speeds quite feasible.

原句Figure 6.66: 3-bit Folding ADC Block Diagram Figure 6.67: Input and Residue Waveforms for 3-Bit Folding ADC ANALOG INPUT SHA MAGAMP 1 MAGAMP 2 GRAY-TO-BINARY CONVERTER OUTPUT REGISTER GRAY CODE REGISTER + - BIT 1 BIT 2 BIT 3 ±VR 3 3 3 001 011 010 110 111 101000 100 INPUT R1 R2 0 0 0 –VR –VR –VR +VR +VR –VR –VR +VR +VR –VR t t t GRAY CODE

原句BASIC LINEAR DESIGN 6.62 Modern IC circuit designs implement the tr ansfer function using current-steering openloop gain techniques which can be made to ope rate much faster.

原句Fully differential stages (including the SHA) also provide speed, lower distortion, and yield 8-bit accurate folding stages with no requirement for thin film resistor laser trimming.

原句An example of a fully differential gain-of-two MagAMP folding stage is shown in Figure 6.68.

原句The differential input signal is applied to the degenerated-emitter differential pair Q1, Q2 and the comparator.

原句The differe ntial input voltage is converted into a differential current which flows in the collector s of Q1, Q2.

原句If +IN is greater than –IN, cascode-connected transistors Q3, Q6 are on, and Q4, Q6 are off.

原句The differential signal currents therefore flow through the collectors of Q3, Q6 into level-shifting transistors Q7, Q8, and into the output load resistors, deve loping the differential output voltage between +OUT and –OUT.

原句The overall differential voltage gain of the circuit is two.

原句If +IN is less than –IN (negative differential input voltage), the comparator changes stage and turns Q4, Q5 on and Q3, Q6 off.

原句The differential signal currents flow from Q5 to Q7 and from Q4 to Q8, thereby maintaining the same relative polarity at the differential output as for a positive differential input voltage.

原句The required offset voltage is developed by adding a current I OFF to the emitter current of Q7 and subtracting it from the emitter current of Q8.

原句The differential residue output voltage of the stage drives the next stage input, and the comparator output represents the Gray code output for the stage.

原句Figure 6.68: A Modern Current-Steering MagAMP Stage VBIAS Q4 Q7 +OUT Q8 -OUT R -IN+IN R R II Q6Q5Q3 Q1 GRAY GRAY Q2 R i+ iVBIAS 2I + IOFF 2I - I OFF + -

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.63 The MagAMP architecture offers lower power and can be extended to sampling rates previously dominated by flash converters.

原句For example, the AD9054A 8-bit, 200 MSPS ADC is shown in Figure 6.69.

原句The first five bits (Gray code) are derived from five differential MagAMP stages.

原句The differential residue output of the fifth MagAMP stage drives a 3-bit flash converter, rather than a single comparator.

原句The Gray-code output of the five MagAMPs and the binary-code output of the 3-bit flash are latched, all converted into binary, and latched again in the output data register.

原句Because of the high data rate, a demultiplexed output option is provided.

原句Figure 6.69: AD9054A 8-bit, 200-MSPS ADC Functional Diagram 5 5 8 ANALOG INPUT SHA MAGAMP 1 MAGAMP 2 MAGAMP 3 MAGAMP 4 MAGAMP 5 3-BIT FLASH ADC BIT 1 GRAY BIT 2 GRAY BIT 3 GRAY BIT 4 GRAY BIT 5 GRAY 3 REGISTER GRAY-TO-BINARY CONVERTER OUTPUT REGISTERS BINARYDIFFERENTIAL OUTPUTS ON BITS 1 - 5 3

原句BASIC LINEAR DESIGN 6.64 Counting and Integrating ADC Architectures Although counting-based ADCs are not well suit ed for high speed app lications, they are ideal for high resolution, low frequency applications, especially when combined with integrating techniques.

原句Figure 6.70: A. H.

原句Reeves' 5-bit Counting ADC The counting ADC technique (see Figure 6.70) basically uses a sampling pulse to take a sample of the analog signal, set an R/S flip -flop, and simultaneou sly start a controlled ramp voltage.

原句The ramp voltage is compared wi th the input, and when they are equal, a pulse is generated which resets the R/S flip-f lop.

原句The output of the flip-flop is a pulse whose width is proportional to the analog signal at the sampling instant.

原句This pulse width modulated (PWM) pulse controls a gated oscill ator, and the number of pulses out of the gated oscillator represents the quantized value of the analog signal.

原句This pulse train can be easily converted to a binary word by driv ing a counter.

原句In Reeves' system, a master clock of 600 kHz was used, and a 100:1 divi der generated the 6-kHz sampling pulses.

原句The system uses a 5-bit counter, and 31 count s (out of the 100 counts between sampling pulses) therefore represents a full-scale signal.

原句The techni que can obviously be extended to higher resolutions.

原句PULSE WIDTH MODULATOR CLOCK 600 kHz 5-BIT COUNTER ÷ 100 SAMPLING PULSE 6 kSPS READ-OUT PULSE 6 kSPS CK RESET VOICE INPUT DATA OUTPUT Adapted from: Alec Harley Reeves, "Electric Signaling System," U.S.

原句Patent 2,272,070, Filed November 22, 1939, Issued February 3, 1942

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.65 Charge Run-Down ADCs The charge run-down ADC architecture show n in Figure 6.71 first samples the analog input and stores the voltage on a fixed capacito r.

原句The capacitor is then discharged with a constant current source, and the time required for complete discharge is measured using a counter.

原句Notice that in this approach, the ov erall accuracy is dependent on the magnitude of the capacitor, the magnitude of the curre nt source, as well as the accuracy of the timebase.

原句Figure 6.71 Charge Run-Down ADC Ramp Run-Up ADCs In the ramp run-up architecture shown in Figur e 6.71, a ramp generator is started at the beginning of the conversion cycle.

原句The counter then measures the time required for the ramp voltage to equal the analog input voltage.

原句The counter output is therefore proportional to the value of the analog input.

原句In an alternate version (shown dotted in Figure 6.72), the ramp voltage generator is replaced by a DAC which is driven by the counter output.

原句The advantage of using the ra mp is that the ADC is always monotonic, whereas overall monotonicity is determined by the DAC when it is used as a substitute.

原句The accuracy of the ramp run-up ADC depends on the accuracy of the ramp generator (or the DAC) as well as the oscillator.

原句TIMER AND CONTROL OSC.

原句COUNTER CK R ANALOG INPUT DIGITAL OUTPUT C I + –

原句BASIC LINEAR DESIGN 6.66 Figure 6.72: Ramp Run-Up ADC Tracking ADCs The tracking ADC architecture shown in Figu re 6.73 continually compares the input signal with a reconstructed representation of the input signal.

原句The up/down counter is controlled by the comparator output.

原句If the analog input exceeds the DAC output, the counter counts up until they are equal.

原句If the DAC output exceed s the analog input, the counter counts down until they are equal.

原句It is evident that if the analog input changes slowly, the counter will follow, and the digital output will remain close to its correct value.

原句If the analog input suddenly under goes a large step change, it will be many hundreds or thousands of clock cycles before the output is again valid.

原句The tracking ADC therefore responds quickly to slowly changi ng signals, but slowly to a quickly changing one.

原句The simple analysis above ignores the beha vior of the ADC when the analog input and DAC output are nearly equal.

原句This will depend on the exact nature of the comparator and counter.

原句If the comparator is a simple one, the DAC output will cycle by 1 LSB from just above the analog input to just below it, and th e digital output will, of course, do the same —there will be 1 LSB of flicker.

原句Note that the output in such a case steps every clock cycle, irrespective of the exact value of analog input, and hence always has unity Mark/Space ratio.

原句In other words, there is no possibility of taking a mean value of the digital output and increasing resolution by oversampling.

原句TIMER AND CONTROL OSC.

原句COUNTER CK R DIGITAL OUTPUT + – * ALTERNATE DAC ANALOG INPUT * RAMP GENERATOR

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.67 Figure 6.73: Tracking ADC A more satisfactory, but more complex arrangement would be to use a window comparator with a window 1-2 LSB wide.

原句When the DAC output is high or low the system behaves as in the previous description, but if the DAC output is within the window, the counter stops.

原句This arrangement e liminates the flicker, provided that the DAC DNL never allows the DAC output to st ep across the window for 1 LSB change in code.

原句Tracking ADCs are not very common.

原句Their sl ow step response makes them unsuitable for many applications, but they do have one asset: their output is continuously available.

原句Most ADCs perform conversions: i.e., on rece ipt of a “start c onvert” command (which may be internally generated), they perform a conversion and, afte r a delay, a result becomes available.

原句Providing that the an alog input changes slowly, the output of a tracking ADC is always available.

原句This is valuable in synchro-to-digital and resolver to digital converters (SDCs and RDCs), and this is the application where tracking ADCs are most often used.

原句Another valuab le characteristic of tracking ADCs is that a fast transient on the analog input causes the output to chan ge only one count.

原句This is very useful in noisy environments.

原句Notice the similarity between a tracking ADC and a successive approximation ADC.

原句Replacing the up/down c ounter with SAR logic yields the architecture for a successive approximation ADC.

原句DIGITAL OUTPUT + – ANALOG INPUT UP/DOWN COUNTER U/D OSC.

原句CK DAC

原句BASIC LINEAR DESIGN 6.68 Voltage-to-Frequency Converters (VFCs) A voltage-to-frequency converter (VFC) is an oscillator whose fr equency is linearly proportional to a control voltage (a high accuracy VCO).

原句The VFC/counter ADC is monotonic and free of missing codes, integrates noise, and can consume very little power.

原句It is also very useful for telemetry applications, since the VFC, which is small, cheap, and low-powered can be mounted on the experimental subject (patient, w ild animal, artillery shell, etc.) and communicate with the co unter by a telemetry link as shown in Figure 6.74.

原句There are two common VFC architectures: the current- steering multivibrator VFC and the charge-balance VFC .

原句The charge-balanced VFC may be made in asynchronous or synchronous (clocked) forms.

原句There are many more VFO (variable fre quency oscillator) architectures, including the ubiquitous 555 timer, but the key feature of VFCs is linearity—few VFOs are very linear. ‹ CONNECTION NEED NOT BE DIRECT ‹ CIRCUIT IS ID EAL FOR TE LEMETRY ANALOG INPUT OUTPUT VFC FREQUENCY COUNTER Figure 6.74: Voltage-to-Frequency Converter (VFC) and Frequency Counter Make a Low Cost, Versatile, High-Resolution ADC The current-steering multivibrator VFC is act ually a current-to-frequency converter rather than a VFC, but, as shown in Figure 6.

原句75, practical circuits invariably contain a voltage-to-current converter at the input.

原句The principle of operation is evident: the current discharges the capacitor until a threshold is reached, and when the capacitor terminals are reversed, the half-cycle repeats itself.

原句Th e waveform across the capacitor is a linear tri-wave, but the waveform on either terminal with respect to ground is the more complex waveform shown.

原句Practical VFCs of this type have lineari ties around 14-bits, and comparable stability, although they may be used in ADCs with hi gher resolutions without missing codes.

原句The performance limits are set by comparator threshold noise, threshold temperature coefficient, and the stability and dielectric absorption (DA) of the capacitor, which is generally a discrete component.

原句The comparator/voltage reference structure shown in the diagram is more of a representation of the function performed than the actual circuit used, which is much more integrated with th e switching, and corres pondingly harder to analyze.

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.69 Figure 6.75: A Current Steering VFC This type of VFC is simple, inexpensive, and low powered, and most run from a wide range of supply voltages.

原句They are ideally suit ed for low cost medium accuracy (12 bit) ADC and data telemetry applications.

原句The charge balance VFC shown in Figure 6.76 is more complex, more demanding in its supply voltage and current requirements, and more accurate.

原句It is capable of 16-bit to 18-bit linearity.

原句Figure 6.76: Charge Balance Voltage-to-Frequency Converter (VFC) + – PRECISION ONE-SHOT I FREQUENCY COUNTER VREF PRECISION CURRENT SOURCE ANALOG INPUT FREQUENCY OUTPUT DIGITAL OUTPUT

原句BASIC LINEAR DESIGN 6.70 The integrator capacitor charges from the si gnal as shown in Figure 6.76.

原句When it passes the comparator threshold, a fixed charge is removed from the capacitor, but the input current continues to flow during the discharg e, so no input charge is lost.

原句The fixed charge is defined by the precision current source and the pulse width of the precision monostable.

原句The output pulse rate is thus accura tely proportional to the rate at which the integrator charges from the input.

原句At low frequencies, the limits on the performan ce of this VFC are set by the stability of the current source and the monostable timing (which depends on the monostable capacitor, among other things).

原句The absolute value and temperature stability of the integration capacitor do not a ffect the accuracy, although its leakage and dielectric absorption (DA) do.

原句At high frequencies, second-order effects, such as switching transients in the integrator and the precision of the monostable when it is retriggered very soon after the end of a pulse, take their toll on accuracy and linearity.

原句The changeover switch in the current source ad dresses the integrator transient problem.

原句By using a changeover switch instead of the on/off switch more common on older VFC designs: (a) there are no on/off transients in the precision current source and (b) the output stage of the integrator sees a constant load—most of the time the current from the source flows directly in the output stage; during charge balance, it still flows in the output stage, but through the integration capacitor.

原句The stability and transient be havior of the precision monosta ble present more problems, but the issue may be avoide d by replacing the monostable with a clocked bistable multivibrator.

原句This arrangement is known as a synchronous VFC or SVFC and is shown in Figure 6.77.

原句Figure 6.77: Synchronous VFC (SVFC) + – I FREQUENCY COUNTER VREF PRECISION CURRENT SOURCE ANALOG INPUT FREQUENCY OUTPUT DIGITAL OUTPUT D FLIP-FLOP D CLOCK INPUT

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.71 The difference from the previous circuit is quite small, but the charge balance pulse length is now defined by two successive edges of the external clock.

原句If this clock has low jitter, the charge will be very accurately defined.

原句The output pulse will also be synchronous with the clock.

原句SVFCs of this t ype are capable of up to 18-bit linearity and excellent temperature stability.

原句This synchronous behavior is convenient in many applications, since synchronous data transfer is often easier to handle than asynchronous.

原句It do es mean, however, that the output of an SVFC is not a pure tone (plus harmonics, of course) like a conventional VFC, but contains components harmonically re lated to the clock frequency.

原句The display of an SVFC output on an oscilloscope is es pecially misleading and is a common cause of confusion—a change of input to a VFC produces a smooth change in the output frequency, but a change to an SVFC produces a change in probability density of output pulses N and N+1 clock cycles after the previous output pulse, which is often misinterpreted as severe jitter and a sign of a faulty device (see Figure 6.78).

原句Another problem with SVFCs is nonlinearity at output freq uencies related to the clock frequency.

原句If we study the transfer characteristic of an SVFC, we find nonlinearities close to sub-harmonics of the clock frequency F C as shown in Figure 6.79.

原句They can be found at FC/3, FC/4, and F C/6.

原句This is due to stray capacitance on the chip (and in the circuit layout!) and coupling the clock signal into the SVFC comparator which causes the device to behave as an injection-lo cked, phase-locked loop (PLL).

原句Th is problem is intrinsic to SVFCs, but is not often serious : if the circuit card is well laid out, and clock amplitude and dv/dts kept as low as pr actical, the effect is a disc ontinuity in the transfer characteristic of less than 8 LSBs (at 18-bit resolution) at F C/3 and FC/4, and less at other sub-harmonics.

原句This is frequently tolerable, since the frequencies where it occurs are known.

原句Of course, if the circui t layout or decoup ling is poor, the effect may be much larger, but this is the fault of poor design and not the SVFC itself.

原句Figure 6.78: VFC and SVFC Waveforms VFC SVFC SVFC CLOCK T VARIES SMOOTHLY WITH INPUT T T1 T2 THE RELATIVE PROBABILITY OF DELAY T1 OR T2 VARIES WITH INPUT, BUT BOTH DELAYS DO OCCUR

原句BASIC LINEAR DESIGN 6.72 ‹ NONLINEARITIES CAUSED BY INJECTION LOCKING DUE TO CLOCK FEEDTHROUGH ‹ SHOULD ONLY BE 6-8 LSBs AT 18-BITS WITH PROPER LAYOUT AND DECOUPLING ‹ NONLINEARITIES OCCUR AT SUBHARMONICS OF THE CLOCK, WHERE FS = FCLOCK/2 Figure 6.79: SVFC Nonlinearity It is evident that the SVFC is quantized, while the basic VFC is not.

原句It does NOT follow from this that the counter/VFC ADC has hi gher resolution (negle cting nonlinearities) than the counter/SVFC ADC, because the clock in the counter also sets a limit to the resolution.

原句When a VFC has a large input, it runs quick ly and (counting for a short time) gives good resolution, but it is hard to get good resolution in a re asonable sample time with a slow-running VFC.

原句In such a case, it may be more practical to meas ure the period of the VFC output (this does not work for an SVFC), but of course the resolution of this system deteriorates as the input (and the frequency) increases.

原句However, if the counter/timer arrangement is made “smart,” it is possibl e to measure the approximate VFC frequency and the exact period of not one, but N cycles (where the value of N is determined by the approximate frequency), and maintain high resolution over a wide range of inputs.

原句The AD1170 modular ADC released in 1986 is an example of this architecture.

原句VFCs have more applications than as a component in ADCs.

原句Since their output is a pulse stream, it may easily be sent over a wide range of transmission media (PSN, radio, optical, IR, ultrasonic, etc.).

原句It need not be received by a counter, but by another VFC configured as a frequency-to-voltage converter (FVC).

原句This gives an analog output, and a VFC-FVC combination is a very useful wa y of sending a precision analog signal across an isolation barrier.

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.73 Dual Slope/Multi-Slope ADCs The dual-slope ADC architecture was truly a breakthrough in ADCs for high resolution applications such as digital voltmeters (DVMs), etc.

原句A simplified diagram is shown in Figure 6.80, and the integrator output waveforms are shown in Figure 6.81.

原句Figure 6.80: Dual slope ADC Figure 6.81: Dual Slope ADC Integrator Output Waveforms The input signal is applied to an integrator; at the same time a counter is started, counting clock pulses.

原句After a predetermined amount of time (T), a refe rence voltage having opposite polarity is applied to th e integrator.

原句At that instan t, the accumulated charge on + – ANALOG INPUT VIN –VREF OSC.

原句TIMER AND CONTROL CK COUNTER R DIGITAL OUTPUT R C 0 Tt x SLOPE = VIN RC SLOPE = VREF RC VIN RC T VREF RC= tx tx = VIN VREF T (CONSTANT SLOPE) t HIGH NORMAL MODE REJECTION AT MULTIPLES OF 1 T

原句BASIC LINEAR DESIGN 6.74 the integrating capacitor is proportional to the average value of the input over the interval T.

原句The integral of the reference is an opposite-going ramp having a slope of V REF/RC.

原句At the same time, the counter is again counti ng from zero.

原句When the integrator output reaches zero, the count is stopped, and the an alog circuitry is reset.

原句Since the charge gained is proportional to V IN · T, and the equal amount of charge lost is proportional to VREF · tx, then the number of counts relative to the full scale count is proportional to t x/T, or VIN/VREF.

原句If the output of the counter is a binary number, it will therefore be a binary representation of the input voltage.

原句Dual-slope integration has many advantages.

原句Conversion accuracy is independent of both the capacitance and the clock frequency, becau se they affect both the up-slope and the down-slope by the same ratio.

原句The fixed input signal integra tion period results in rejection of noise frequencies on the analog input that have periods that are equal to or a sub-multiple of the integration time T.

原句Proper choice of T can therefore result in excellent rejection of 50-Hz or 60-Hz line ripple as shown in Figure 6.82.

原句Errors caused by bias currents and the offset voltages of the integrating amplifier and the comparator as well as gain errors can be cancelled by using additi onal charge/discharge cycles to measure “zero” and “full-scale” a nd using the results to digitally correct the initial measurement, as in the quad-slope architecture.

原句Figure 6.82: Frequency Response of Integrating ADC

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.75 The triple-slope architecture retains the a dvantages of the dual-slope, but greatly increases the conversion speed at the cost of added complexity.

原句The increase in conversion speed is achieved by accomplishing the reference integration (ramp-down) at two distinct rates: a high-speed rate, and a “vernier” lower speed rate.

原句The counter is likewise divided into two sections, one for th e MSBs and one for the LSBs.

原句In a properly designed triple-slope convert er, a significant increase in speed can be achieved while retaining the inherent linearity, differentia l linearity, and stability characteristics associated with dual-slope ADCs.

原句BASIC LINEAR DESIGN 6.76 Resolver-to-Digital Converters (RDCs) and Synchros Machine-tool and robotics manufacturers have increasingly turned to resolvers and synchros to provide accurate a ngular and rotational information.

原句These devices excel in demanding factory applications requiring small size, long-term reliability, absolute position measurement, high accuracy, and low noise operation.

原句A diagram of a typical synchro and resolver is shown in Figure 6.83.

原句Both synchros and resolvers employ single-winding roto rs that revolve inside fixed stators.

原句In the case of a simple synchro, the stator has three windi ngs oriented 120º apar t and electrically connected in a Y-connection.

原句Resolvers differ from synchros in that their stators have only two windings oriented at 90º.

原句Figure 6.83: Synchros and Resolvers Because synchros have three stator coils in a 120º orientation, they are more difficult than resolvers to manufacture and are therefore more costly.

原句T oday, synchros find decreasing use, except in certain military and avionic retrofit applications.

原句Modern resolvers, in contrast, are available in a brushless form that employ a transformer to couple the rotor signals from the stator to the rotor.

原句The pr imary winding of this transformer resides on the stator, and the s econdary on the rotor.

原句Other resolvers use more traditional brushes or slip rings to couple the signal into the rotor winding.

原句Brushless resolvers are more rugged than synchros because there are no brushes to break or dislodge, and the life of a brushless reso lver is limited only by its bearings.

原句Most resolvers are specified to work over 2 V to 40 V rms and at frequencies from 400 Hz to 10 kHz.

原句Angular accuracies range from 5 arc-minutes to 0.5 arc- minutes.

原句(There are R1 R2 S1 S2 S3 R1 R2 S1 S2 S3 S4 S1 TO S3 = V sin ωt sin θ S3 TO S2 = V sin ωt sin (θ + 120°) S2 TO S1 = V sin ωt sin (θ + 240°) S1 TO S3 = V sin ωt sin θ S4 TO S2 = V sin ωt sin (θ + 90°) = V sin ωt cos θ ROTOR ROTOR STATOR STATOR ROTOR STATOR SYNCHRO RESOLVER V sin ωt V sin ωt θ

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.77 60 arc-minutes in one degree, and 60 arc-seconds in one arc-minute.

原句Hence, one arc-minute is equal to 0.0167 degrees).

原句In operation, synchros and resolvers resemble rotating transformers.

原句The rotor winding is excited by an ac reference voltage, at frequenc ies up to a few kHz.

原句The magnitude of the voltage induced in any stator winding is proportional to the sine of the angle, θ, between the rotor coil axis and the stator coil axis.

原句In the case of a synchr o, the voltage induced across any pair of stator terminals will be the vector sum of the voltages across the two connected coils.

原句For example, if the rotor of a synchro is excited with a reference voltage, Vsin ωt, across its terminals R1 and R2, then the stator's terminal will see voltages in the form: S1 to S3 = V sinωt sinθ Eq.

原句6.1 S3 to S2 = V sinωt sin (θ + 120º) Eq.

原句6.2 S2 to S1 = V sinωt sin (θ + 240º), Eq.

原句6.3 where θ is the shaft angle.

原句In the case of a resolver, with a rotor ac reference voltage of Vsin ωt, the stator's terminal voltages will be: S1 to S3 = V sinωt sin θ Eq.

原句6.4 S4 to S2 = V sinωt sin(θ + 90º) = V sinωt cosθ.

原句Eq. 6.5 It should be noted that th e 3-wire synchro out put can be easily converted into the resolver-equivalent format using a Scott-T tr ansformer.

原句Therefore, the following signal processing example describes only the resolver configuration.

原句A typical resolver-to-digital converter (RDC) is shown func tionally in Figure 6.84.

原句The two outputs of the resolver are applied to co sine and sine multipliers.

原句These multipliers incorporate sine and cosine lookup tables and function as multiplying digital-to-analog converters.

原句Begin by assuming that the current state of the up/down counter is a digital number representing a trial angle, ϕ.

原句The converter seeks to ad just the digital angle, ϕ, continuously to become equal to, and to track θ, the analog angle being measured.

原句The resolver's stator output voltages are written as: V1 = V sinωt sinθ Eq.

原句6.6 V2 = V sinωt cosθ Eq.

原句6.7 where θ is the angle of the resolver ’s rotor.

原句The digital angle ϕ is applied to the cosine multiplier, and its cosine is multiplied by V1 to produce the term: V sinωt sinθ cosϕ.

原句Eq. 6.8 The digital angle ϕ is also applied to the si ne multiplier and multiplied by V 2 to product the term: V s i n ωt cosθ sinϕ.

原句Eq. 6.9

原句BASIC LINEAR DESIGN 6.78 Figure 6.84: Resolver-to-Digital Converter (RDC) These two signals are subtracted from each other by the error amplifier to yield an ac error signal of the form: V s i n ωt [sinθ cosϕ – cosθ sinϕ].

原句Eq. 6.10 Using a simple trigonometric identity, this reduces to: V s i n ωt [sin (θ –ϕ)].

原句Eq. 6.11 The detector synchronously demodulates this ac error signal, using the resolver’s rotor voltage as a reference.

原句This results in a dc error signal proportional to sin(θ–ϕ).

原句The dc error signal feeds an integrator, the output of which drives a voltage-controlledoscillator (VCO).

原句The VCO, in turn, cause s the up/down counter to count in the proper direction to cause: S i n ( θ – ϕ) → 0.

原句Eq. 6.12 When this is achieved, θ – ϕ → 0, Eq.

原句6.13 and therefore ϕ = θ Eq.

原句6.14 COSINE MULTIPLIER SINE MULTIPLIER DETECTOR INTEGRATOR UP / DOWN COUNTER VCO V sin ωt sin θ V sin ωt cos θ V sin ωt sin θ cos ϕ V sin ωt cos θ sin ϕ _ + V sin ωt [sin (θ – ϕ )] ERROR V sin ωt ROTOR REFERENCE STATOR INPUTS LATCHES K sin (θ – ϕ ) ϕ ϕ = DIGITAL ANGLE ϕ VELOCITY WHEN ERROR = 0, ϕ = θ ± 1 LSB ϕ

原句CONVERTERS ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.79 to within one count.

原句Hence, the counter’s digital output, ϕ, represents the angle θ.

原句The latches enable this data to be transferred externally without interrupting the loop's tracking.

原句This circuit is equivalent to a so-called type -2 servo loop, because it has, in effect, two integrators.

原句One is the counter, which accumulates pulses; the other is the integrator at the output of the detector.

原句In a type-2 servo loop with a constant rotational velocity input, the output digital word continuously follows, or tr acks the input, withou t needing externally derived convert commands, and with no steady state phase lag between the digital output word and actual shaft angle.

原句An error signa l appears only during periods of acceleration or deceleration.

原句As an added bonus, the tracking RDC provides an analog dc output voltage directly proportional to the shaft's rotational velocity.

原句This is a useful feature if velocity is to be measured or used as a stabilization term in a servo system, and it makes tachometers unnecessary.

原句Since the operation of an RDC depends only on the ratio between input signal amplitudes, attenuation in the lines connecting them to resolvers doesn’t substantially affect performance.

原句For similar reasons, thes e converters are not greatly susceptible to waveform distortion.

原句In fact, they can opera te with as much as 10% harmonic distortion on the input signals; some applications actua lly use square-wave references with little additional error.

原句Tracking ADCs are therefore ideally suited to RDCs.

原句While other ADC architectures, such as successive approximation, could be used, the tracking c onverter is the most accurate and efficient for this application.

原句Because the tracking converter doubly integrates its error signal, the device offers a high degree of noise immunity (12 dB per octave rolloff).

原句The net area under any given noise spike produces an error.

原句However, typical i nductively coupled noise spikes have equal positive and negative going waveforms.

原句When integrated, this results in a zero net error signal.

原句The resulting noise immunity, combin ed with the converter ’s insensitivity to voltage drops, lets the user locate the conve rter at a considerable distance from the resolver.

原句Noise rejection is further enhanced by the detector's reject ion of any signal not at the reference frequency, such as wideband noise.

原句The AD2S90 is one of a number of integr ated RDCs offered by Analog Devices.

原句The general architecture is similar to that of Figure 6.83.

原句Further details on synchro and resolver-to-digital converters can be found in the references.

原句Syncros and resolvers are also discussed in Chapter 3 (section 3.1)

原句BASIC LINEAR DESIGN 6.80 REFERENCES: ADC ARCHITECTURES 1.

原句Walt Kester, Editor, Amplifier Applications Guide , Analog Devices, 1992, ISBN-0-916550-10-9, Chapter 10.

原句(An excellent discussion by James Bryant on the use of op amps as comparators).

原句2. James N. Giles, “High Speed Transistor Difference Amplifier,” U.S.

原句Patent 3,843,934 , filed January 31 1973, issued October 22, 1974.

原句(Describes one of the first hi gh-speed ECL comparators, the AM685).